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d a t a sh eet integrated circuits saa6713h xga dual input flat panel controller product speci?cation supersedes data of 2002 jul 16 2004 apr 05
2004 apr 05 2 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 programming registers 7.2 device id 7.3 initialization 7.4 clock management 7.5 synchronization pulse distribution 7.6 interrupt generation 7.7 triple analog-to-digital converter 7.8 dvi interface 7.9 input interface 7.10 colour processing 7.11 rgb mode detection and auto-adjustment 7.12 decoupling fifo 7.13 scaling 7.14 on screen display 7.15 colour look-up table 7.16 dithering unit 7.17 output interface 8 boundary scan test 8.1 initialization of boundary scan circuit 8.2 device identification codes 9 limiting values 10 thermal characteristics 11 characteristics 12 timing characteristics 13 application information 14 package outline 15 soldering 15.1 introduction to soldering surface mount packages 15.2 reflow soldering 15.3 wave soldering 15.4 manual soldering 15.5 suitability of surface mount ic packages for wave and reflow soldering methods 16 data sheet status 17 definitions 18 disclaimers 19 purchase of philips i 2 c components
2004 apr 05 3 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 1 features integrated triple analog-to-digital converter (adc) for rgb analog sampling up to 110 mhz integrated pll for dot clock recovery integrated single channel digital visual interface (dvi) (1) compliant digital serial interface up to 110 mhz dot clock integrated composite sync slicer high-bandwidth digital content protection (hdcp) (2) integrated sync-on-green separation support of super extended graphics adapter (sxga) input mode independent horizontal and vertical arbitrary ratio up and downscaling video mode detection auto-adjustment support for sampling phase and frequency, picture alignment and colour alignment advanced colour adjustment integrated on screen display (osd) controller with predefined and programmable font and bit-mapped graphics, as well as a hardware overlay cursor 10-bit gamma correction support for 6-bit and 8-bit panels by temporal dithering freely programmable output timing supports displays of virtually any manufacturer directly interfaces row and column drivers (tcon), versatile timing generation programmable output pin ordering adjustable output pin ordering high-speed i 2 c-bus interface up to 3.4 mbits/s event driven interrupt generation for easy interfacing with microcontroller software. 2 general description the saa6713h is a dual input single-chip thin film transistor (tft) display controller ic with analog vga and digital dvi 1.0 standard input capabilities. additionally, the saa6713h includes a wide range of functions for processing and the measurement of incoming rgb data according to the requirements of an xga tft display. covered functions are accurate measurements for the horizontal and vertical input frequencies to determine the incoming video mode and advanced auto-adjustment features that provide all data for a fast and accurate adjustment of frequency, phase and gain settings. both units are able to generate interrupts for easy interfacing with a system microcontroller with separately maskable interrupt conditions. the input section handles incoming data up to sxga resolution that can be downscaled individually in width and height to fit to the connected panel resolution. independent horizontal and vertical upscaling with enhanced programmable filter possibilities provides the ics core functionality of high-quality scaling. picture quality is further supported by an enhanced colour management including a 10-bit gamma correction function. a sophisticated dithering unit allows the use of low-end 6-bit panels while keeping up the high quality image impression. an advanced osd generator is integrated with a fixed 12 18 rom font consisting of 179 ansi characters, 77 japanese characters, 48 multicolour icons and 48 single colour icons. in addition to these fixed size characters another 112 different border characters can be generated in any desired font size between 8 8 and 32 32 pixels. another 38 special characters are provided particularly for multicolour slider icons that can be parametrized in size and style. for higher flexibility of the osd appearance a downloadable mixed multicolour or single colour font with any programmable character size between 8 8to32 32 pixels and up to four colours per character can be used and displayed together with the predefined rom characters. a special bitmap organized graphical osd with up to 16 individual colours allows to include graphic items like company logos, while a double buffered osd cursor gives the ability to use animated pointers within an on screen menu. the panel timing interface can not only drive todays common timing controller based panel interfaces, but it has also the capability to directly drive the row and column drivers of a panel itself. an adjustable output pin ordering guarantees easy board layout with any type of panel connector. (1) dvi speci?cation published by digital display working group (ddwg) promoters and may have related patents and/or patent applications. (2) hdcp is software designed by intel/silicon image. all trademark rights belong to the respective producers.
2004 apr 05 4 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h the saa6713h represents the first fully integrated single-chip solution for low-end monitors, offering both high quality scaling and an advanced osd generator. 3 quick reference data note 1. pins hsync, vsync, sda and scl are 5 v tolerant inputs. 4 ordering information symbol parameter conditions min. typ. max. unit v ddd(ic) digital supply voltage for internal core on pins v ddd(ic1) to v ddd(ic6) 2.3 2.5 2.7 v v dda analog supply voltage on pins v dda(r) , v dda(g) , v dda(b) , v dda(adc)(r) , v dda(adc)(g) , v dda(adc)(b) and v dda(dvi1) to v dda(dvi3) 2.3 2.5 2.7 v v dd(pll) , v ddd(pll) , v dda(pll) supply voltage for pll on pins v dd(pll)(dvi) , v dd(pll)(p) , v dda(pll)(s) and v ddd(pll)(s) 2.3 2.5 2.7 v v dda(ib) analog supply voltage for input buffer on pin v dda(ib) 2.7 3.0 3.3 v v ddd(ep) external digital pad supply voltage for pins v ddd(ep1) to v ddd(ep10) 3.0 3.3 3.6 v v dda(ep) external analog pad supply voltage for pin v dda(ep) 3.0 3.3 3.6 v i dd(tot) total supply current - 410 - ma v i input voltage note 1 lvttl compatible v o output voltage for tft port cmos compatible t amb ambient temperature 0 - 70 c type number package name description version saa6713h/v1 qfp160 plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 28 3.4 mm; high stand-off height sot322-2
2004 apr 05 5 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram handbook, full pagewidth i 2 c-bus interface 1 configuration data csg2/a0 scl sda csg4/a1 hsda tdo int hscl jtag interface test control signals trst tms tdi rst tck control unit control signals pclk, csg0 to csg9, inva, invb, pwm, outen pa0 to pa7, pb0 to pb7, pc0 to pc7 pd0 to pd7, pe0 to pe7, pf0 to pf7 output interface input interface dithering upscaler osd down- scaler hdcp rin sogin hsync vclk clk vsync gin bin rbias rxcp, rxcn, rx0p, rx0n, rx1p, rx1n, rx2p, rx2n auto- adjustment saa6713h mode detection sync selection and csync decoder sync- on- green slicer dvi 1.0 interface 3 adc clock generator: panel clock pll sample clock pll phase shift colour look-up table rgb data 3 10-bit rgb data 3 8-bit rgb data 3 8-bit rgb data 3 8-bit rgb data 3 8-bit data enable syncs panel clock sample clock syncs syncs syncs rgb data 3 6-bit or 3 8-bit rgb data 3 6-bit or 3 8-bit rgb data 3 6-bit or 3 8-bit panel control signals mhc211 decoupling fifo i 2 c-bus interface 2 hdcp data fig.1 block diagram.
2004 apr 05 6 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 6 pinning symbol pin (1) type description v ssa(bias)(b) 1 - analog ground for bias; blue channel bin 2 a blue colour signal input v dda(adc)(b) 3 - analog supply voltage for adc; blue channel (2.5 v) ref_b 4 a blue channel reference input v ssa(adc)(b) 5 - analog supply ground for adc; blue channel v dda(b) 6 - analog supply voltage; blue channel (2.5 v) v ssa(b) 7 - analog supply ground; blue channel v dda(ib) 8 - analog supply voltage for input buffers (3.0 v) rbias 9 a external bias resistor input v ssa(bias)(sog) 10 - analog ground for bias; sync-on-green sogin 11 a sync-on-green input v ssa(bias)(g) 12 - analog ground for bias; green channel gin 13 a green colour signal input v dda(adc)(g) 14 - analog supply voltage for adc; green channel (2.5 v) ref_g 15 a green channel reference input v ssa(adc)(g) 16 - analog supply ground for adc; green channel v dda(g) 17 - analog supply voltage; green channel (2.5 v) v ssa(g) 18 - analog supply ground; green channel v ssa(bias)(r) 19 - analog ground for bias; red channel rin 20 a red colour signal input v dda(adc)(r) 21 - analog supply voltage for adc; red channel (2.5 v) ref_r 22 a red channel reference input v ssa(adc)(r) 23 - analog supply ground for adc; red channel v dda(r) 24 - analog supply voltage; red channel (2.5 v) v ssa(r) 25 - analog supply ground; red channel v dda(dvi1) 26 - analog supply voltage 1 for dvi (2.5 v) rx2p 27 a differential red channel positive input rx2n 28 a differential red channel negative input v ssa(dvi1) 29 - analog supply ground 1 for dvi rx1p 30 a differential green channel positive input rx1n 31 a differential green channel negative input v dda(dvi2) 32 - analog supply voltage 2 for dvi (2.5 v) rx0p 33 a differential blue channel positive input rx0n 34 a differential blue channel negative input v ssa(dvi2) 35 - analog supply ground 2 for dvi rxcn 36 a differential clock negative input rxcp 37 a differential clock positive input v dda(dvi3) 38 - analog supply voltage 3 for dvi (2.5 v) v ss(pll)(dvi) 39 - supply ground for dvi phase locked loop v dd(pll)(dvi) 40 - supply voltage for dvi phase locked loop (2.5 v)
2004 apr 05 7 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h sda 41 i/o serial data input or output (i 2 c-bus) scl 42 i serial clock input (i 2 c-bus) hsda 43 i/o hdcp serial data input or output (i 2 c-bus) hscl 44 i hdcp serial clock input (i 2 c-bus) v ssd(ic1) 45 - internal digital core supply ground 1 v ddd(ic1) 46 - internal digital core supply voltage 1 (2.5 v) clk 47 i master clock input v ssd(ep1) 48 - external digital pad supply ground 1 v ddd(ep1) 49 - external digital pad supply voltage 1 (3.3 v) int 50 o microcontroller interrupt output (active low) rst 51 i master reset input (active low) pclk 52 o panel clock output csg0 53 o control signal generator 0 output csg1 54 o control signal generator 1 output csg2/a0 55 i/o control signal generator 2 output (csg2) or i 2 c-bus slave address input, latched via hardware reset (a0) v ssd(ep2) 56 - external digital pad supply ground 2 v ddd(ep2) 57 - external digital pad supply voltage 2 (3.3 v) pa0 58 i/o panel data port a bit 0 pa1 59 i/o panel data port a bit 1 pa2 60 i/o panel data port a bit 2 pa3 61 i/o panel data port a bit 3 pa4 62 i/o panel data port a bit 4 pa5 63 i/o panel data port a bit 5 pa6 64 i/o panel data port a bit 6 pa7 65 i/o panel data port a bit 7 v ssd(ep3) 66 - external digital pad supply ground 3 v ddd(ep3) 67 - external digital pad supply voltage 3 (3.3 v) pb0 68 i/o panel data port b bit 0 pb1 69 i/o panel data port b bit 1 v ssd(ic2) 70 - internal digital core supply ground 2 v ddd(ic2) 71 - internal digital core supply voltage 2 (2.5 v) pb2 72 i/o panel data port b bit 2 pb3 73 i/o panel data port b bit 3 pb4 74 i/o panel data port b bit 4 pb5 75 i/o panel data port b bit 5 pb6 76 i/o panel data port b bit 6 pb7 77 i/o panel data port b bit 7 v ssd(ep4) 78 - external digital pad supply ground 4 v ddd(ep4) 79 - external digital pad supply voltage 4 (3.3 v) pc0 80 i/o panel data port c bit 0 symbol pin (1) type description
2004 apr 05 8 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h pc1 81 i/o panel data port c bit 1 pc2 82 i/o panel data port c bit 2 pc3 83 i/o panel data port c bit 3 pc4 84 i/o panel data port c bit 4 pc5 85 i/o panel data port c bit 5 pc6 86 i/o panel data port c bit 6 pc7 87 i/o panel data port c bit 7 v ssd(ep5) 88 - external digital pad supply ground 5 v ddd(ep5) 89 - external digital pad supply voltage 5 (3.3 v) v ssd(ic3) 90 - internal digital core supply ground 3 v ddd(ic3) 91 - internal digital core supply voltage 3 (2.5 v) pd0 92 o panel data port d bit 0 pd1 93 o panel data port d bit 1 pd2 94 o panel data port d bit 2 pd3 95 o panel data port d bit 3 pd4 96 o panel data port d bit 4 pd5 97 o panel data port d bit 5 pd6 98 o panel data port d bit 6 pd7 99 o panel data port d bit 7 v ssd(ep6) 100 - external digital pad supply ground 6 v ddd(ep6) 101 - external digital pad supply voltage 6 (3.3 v) v ssd(ic4) 102 - internal digital core supply ground 4 v ddd(ic4) 103 - internal digital core supply voltage 4 (2.5 v) pe0 104 o panel data port e bit 0 pe1 105 o panel data port e bit 1 pe2 106 o panel data port e bit 2 pe3 107 o panel data port e bit 3 pe4 108 o panel data port e bit 4 pe5 109 o panel data port e bit 5 pe6 110 o panel data port e bit 6 pe7 111 o panel data port e bit 7 v ssd(ep7) 112 - external digital pad supply ground 7 v ddd(ep7) 113 - external digital pad supply voltage 7 (3.3 v) pf0 114 o panel data port f bit 0 pf1 115 o panel data port f bit 1 pf2 116 o panel data port f bit 2 pf3 117 o panel data port f bit 3 pf4 118 o panel data port f bit 4 pf5 119 o panel data port f bit 5 pf6 120 o panel data port f bit 6 pf7 121 o panel data port f bit 7 symbol pin (1) type description
2004 apr 05 9 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h v ssd(ic5) 122 - internal digital core supply ground 5 v ddd(ic5) 123 - internal digital core supply voltage 5 (2.5 v) v ssd(ep8) 124 - external digital pad supply ground 8 v ddd(ep8) 125 - external digital pad supply voltage 8 (3.3 v) csg3 126 o control signal generator 3 output csg4/a1 127 i/o control signal generator 4 output (csg4) or i 2 c-bus slave address input, latched via hardware reset (a1) csg5 128 o control signal generator 5 output csg6 129 o control signal generator 6 output csg7 130 o control signal generator 7 output v ssd(ep9) 131 - external digital pad supply ground 9 v ddd(ep9) 132 - external digital pad supply voltage 9 (3.3 v) csg8 133 o control signal generator 8 output csg9 134 o control signal generator 9 output vclk 135 i/o sample clock input or output; con?gurable as output if generated internally inva 136 o data inversion output of ports a, b and c invb 137 o data inversion output of ports d, e and f outen 138 o output enable status output pwm 139 o pulse width modulation for control of backlight brightness output vsync 140 i/o vertical sync input or output; con?gurable as output if decoded from dvi or composite sync hsync 141 i horizontal and composite sync input v ssd(ep10) 142 - external digital pad supply ground 10 v ddd(ep10) 143 - external digital pad supply voltage 10 (3.3 v) v ssd(ic6) 144 - internal digital core supply ground 6 v ddd(ic6) 145 - internal digital core supply voltage 6 (2.5 v) v ss(pll)(p) 146 - supply ground for panel clock phase locked loop v dd(pll)(p) 147 - supply voltage for panel clock phase locked loop (2.5 v) n.c. 148 - do not connect v ssa(pll)(s) 149 - analog supply ground for sample clock phase locked loop v dda(pll)(s) 150 - analog supply voltage for sample clock phase locked loop (2.5 v) v ssd(pll)(s) 151 - digital supply ground for sample clock phase locked loop v ddd(pll)(s) 152 - digital supply voltage for sample clock phase locked loop (2.5 v) trst 153 i test reset input for boundary scan test (active low); note 2 tck 154 i test clock input for boundary scan test; note 2 tdi 155 i test data input for boundary scan test; note 2 tms 156 i test mode select input for boundary scan test or scan test; note 2 tdo 157 o test data output for boundary scan test symbol pin (1) type description
2004 apr 05 10 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h notes 1. for pin type description see table 1. 2. for board design without boundary scan implementation connect pins trst, tck, tdi and tms to ground. table 1 pin type description v ssa(ep) 158 - external analog pad supply ground v dda(ep) 159 - external analog pad supply voltage (3.3 v) agcana 160 - analog test pad (should be connected to analog ground for application) type description a analog input i digital input o digital output i/o digital input or output symbol pin (1) type description
2004 apr 05 11 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth v ssa(bias)(b) bin v dda(adc)(b) ref_b v ssa(adc)(b) v dda(b) v ssa(b) v dda(ib) rbias v ssa(bias)(sog) sogin v ssa(bias)(g) gin v dda(adc)(g) ref_g v ssa(adc)(g) v dda(g) v ssa(g) v ssa(bias)(r) rin v dda(adc)(r) ref_r v ssa(adc)(r) v dda(r) v ssa(r) v dda(dvi1) rx2p rx2n v ssa(dvi1) rx1p rx1n v dda(dvi2) rx0p rx0n v ssa(dvi2) rxcn rxcp v dda(dvi3) v ss(pll)(dvi) v dd(pll)(dvi) pf6 pf5 pf4 pf3 pf2 pf1 pf0 v ddd(ep7) v ssd(ep7) pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 v ddd(ic4) v ssd(ic4) v ddd(ep6) v ssd(ep6) pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 v ddd(ic3) v ssd(ic3) v ddd(ep5) v ssd(ep5) pc7 pc6 pc5 pc4 pc3 pc2 pc1 agcana v dda(ep) v ssa(ep) tdo tms tdi tck trst v ddd(pll)(s) v ssd(pll)(s) v dda(pll)(s) v ssa(pll)(s) n.c. v dd(pll)(p) v ss(pll)(p) v ddd(ic6) v ssd(ic6) v ddd(ep10) v ssd(ep10) hsync vsync pwm outen invb inva vclk csg9 csg8 v ddd(ep9) v ssd(ep9) csg7 csg6 csg5 csg4/a1 csg3 v ddd(ep8) v ssd(ep8) v ddd(ic5) v ssd(ic5) pf7 sda scl hsda hscl v ssd(ic1) v ddd(ic1) clk v ssd(ep1) v ddd(ep1) int rst pclk csg0 csg1 csg2/a0 v ssd(ep2) v ddd(ep2) pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 v ssd(ep3) v ddd(ep3) pb0 pb1 v ssd(ic2) v ddd(ic2) pb2 pb3 pb4 pb5 pb6 pb7 v ssd(ep4) v ddd(ep4) pc0 mhc212 saa6713h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 fig.2 pin configuration.
2004 apr 05 12 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7 functional description in this chapter detailed information for the general configuration of the saa6713h is provided as well as detailed background information belonging to certain submodules of the device. due to the high complexity of the device functionality this section should be studied very carefully. 7.1 programming registers 7.1.1 c onfiguration parameter mapping the saa6713h operation is controlled by configuration parameters, that can be multiple-bit words or consist of only a single bit. the configuration parameters are mapped to bits of the 8 bit i 2 c-bus programming registers, that are accessible via the i 2 c-bus interface. read-out data such as measurement results or interrupt states is mapped to readable i 2 c-bus registers. the i 2 c-bus registers are organized in pages. generally, a register can only be accessed if the particular page is activated with the exception of global registers, so non-global registers are addressed by the i 2 c-bus subaddress in combination with the matching active page, but global registers are addressed by the subaddress independently of the active page. the global registers are mapped to i 2 c-bus subaddresses f8h to ffh. the active page is defined by page_select at subaddress ffh. in general, registers belonging to the same functional unit are mapped onto the same page. the i 2 c-bus register pages are shown in table 2. table 2 i 2 c-bus register pages 7.1.2 i 2 c- bus interface the i 2 c-bus serial interface consists of two pins: the serial clock pin scl and the serial data pin sda. 7.1.2.1 transmission bit rate the i 2 c-bus interface supports transmission speeds of up to 3.4 mbits/s, given that a minimum system clock rate is provided. the required system clock rate depends on the target i 2 c-bus bit rate, which is the clock rate applied to pin scl, and the spike suppression mode selected by iic_spike_mode in register iic_mode (03h at page 0) as shown in table 3. if iic_spike_mode is set to 2, a high oversampling rate is used and the most effective spike suppression is provided. table 3 i 2 c-bus spike suppression modes 7.1.2.2 i 2 c-bus transmission timing the saa6713h only operates as a slave and the clock pin scl is exclusively input. data is transmitted and received at i/o pin sda. the sda is an open-drain stage with an external pull-up resistor. when a logic 0 is applied, the bus is pulled to low-level by the output buffer. when a logic 1 is applied, the output buffer switches to 3-state and the pull-up resistor pulls the bus up to high-level. data transfers are initiated by an i 2 c-bus master device by sending the start condition, which is a change from high-to-low level at sda when scl is at high-level (see fig.3). data is transmitted byte wise. data changes on sda are allowed only when scl is at low-level and data is sampled on the positive edge of scl. the first transmitted byte is the recipients i 2 c-bus device address and the data transfer direction bit. all byte transfers are acknowledged by the recipient by pulling sda to low-level for the following cycle. page functional unit 0 control unit and clock generator 1 adc control 2 mode detection 3 auto-adjustment 4 input interface and picture generator 5 colour processing 6 decoupling fifo 7 scalers 8 osd 9 osd colour de?nition 10 gamma correction and dithering 11 tft output interface iic_spike_ mode[1:0] system clock description 00 >6 i 2 c-bus bit rate 2-out-of-2 ?lter 01 >6 i 2 c-bus bit rate 2-out-of-3 majority ?lter 10 >16 i 2 c-bus bit rate 4-out-of-4 ?lter 11 not used
2004 apr 05 13 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h if the write mode was selected, the bus master sends a byte containing the starting subaddress and then a series of data bytes. in case the read mode was selected, the addressed slave returns a series of data bytes. a read transfer is preceded by a write transfer that transmits the starting subaddress. data transfers are aborted by the stop condition, when sda is changed by the master from low-to-high level when scl is at high-level (see fig.4). 7.1.2.3 i 2 c-bus device address bits a0 and a1 of the i 2 c-bus device address are externally selected by two input pins csg2/a0 and csg4/a1. the device address (byte) of the saa6713h is shown in table 4. table 4 i 2 c-bus device address byte the four possible i 2 c-bus device addresses are selected via resistor strapping at pins csg2/a0 and csg4/a1 (see table 5). during the hardware reset (pin rst = low), pins csg2/a0 and csg4/a1 are 3-stated. their status at the trailing edge of signal rst will latch and determine the device address. pull-up and pull-down resistors (4.7 k w suggested) select the address. an internal pull-down resistance of approximately 100 k w is provided and eliminates potentially the need for any external strapping resistor. after reset, the pins carry the output of the programmable signal generators. table 5 device address selection msb lsb device address bits r/ w 01110a1a00/1 i 2 c-bus device address strapping resistor pin csg4/a1 pin csg2/a0 70h pull-down pull-down 72h pull-down pull-up 74h pull-up pull-down 76h pull-up pull-up fig.3 start of a data transfer. handbook, full pagewidth mhb248 scl sda a4 a1 a2 a3 a6 a5 ack r/w a0 r5 r7 r6 start condition acknowledge fig.4 end of a data transfer. handbook, full pagewidth mhb249 scl sda d7 d4 d5 d6 d1 d0 ack d2 d3 a/a d1 d0 stop condition acknowledge/ not acknowledge
2004 apr 05 14 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.1.2.4 i 2 c-bus subaddress when transmitting a series of data bytes, after a data byte has been written or read, the subaddress for the following byte is automatically updated to allow burst access. during burst access a sequence of data bytes is written or read without repeated device or subaddressing. in general, the i 2 c-bus auto-increment feature uses the next higher subaddress as the succeeding bytes subaddress. auto-incrementing is suppressed for several addresses that provide access to the on-chip parameter ram. in the event of upscaler register usc_lut_data (02h at page 7) subsequent data is written to the same subaddress and the scaling curve ram address is incremented instead. for osd registers osdt_prop2 to osdt_prop0, osdb_def and osdp_def (0fh to 11h, 31h and 4ch at page 8) and colour look-up table register cl_value_lo (03h at page 10) different subaddress update modes are selectable and are described in the respective subsection. 7.1.2.5 multiple byte parameters parameters or read-out data words consisting of more than 8 bits are mapped into the address space in the order highest byte at the lowest address to lowest byte at the highest address. multiple byte configuration parameters have to be written lowest address first and only become effective, once the byte of the highest address was written. multiple byte read registers have to be read-out in the same order. 7.1.2.6 i 2 c-bus test register register iic_test (02h at page 0) is a read and write register that can be used to verify correct operations of the i 2 c-bus. any programmed value can be read back. 7.1.3 i 2 c- bus register listing the global registers are listed in table 6. the page-mapped registers are listed for each register page in tables 7 to 17.
2004 apr 05 15 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 6 global con?guration registers table 7 general control con?guration registers (page 0); note 1 register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 global control: fah to ffh gc_misc0 fah w 00h avi_ noclamp_ sog_en dvi_lock_ sgnl_sel reserved dvi_acc_ phase_diff dvi_phase_adj_ threshold gc_misc1 fbh w ffh avi_ noclamp_ pol reserved dvi_ delock_int_ mdd_en reserved gc_reset fch w 1fh reset_ csdec_n reset_ dviclk reset_fclk reset_bclk reset_oif gc_int_mask fdh w - 0 - 0 0000 int_iif_en int_mode_ en int_auto_ en int_?fo_en int_osd_en int_oif_en gc_int_clr feh w - 1 - 1 1111 int_iif_clr int_mode int_auto int_?fo int_osd int_oif gc_int_stat feh r - 0 - 0 0000 int_iif_stat int_mode int_auto int_?fo int_osd int_oif gc_page ffh r/w ---- 0000 page_select[3:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 device identi?cation: 00h to 03h dev_id_hi 00h r 13h dev_id[15:8] dev_id_lo 01h r 1ch dev_id[7:0] iic_test 02h r/w 00h iic_test[7:0] iic_mode 03h w ---- -- 00 iic_spike_mode[1:0] clock distribution: 10h to 12h cd_clk_en 10h w -- 00 0000 cfgclk_on osd_ cfgclk_on aaclk_on dscclk_on uscclk_on osdclk_on cd_clk_auto 11h w ---- 1111 aaclk_auto dscclk_ auto uscclk_ auto osdclk_ auto cd_clk_mux 12h w -- 11 0110 vclk_in_en cfgclk_ select ?fo_fclk frontend_ bclk bclk_in_en clk_div4 sync distribution: 18h and 19h sync_sel 18h w --- 0 0000 hs_regen_ in_en vsync_out_ en cs_dvi_de sog_out_ en sog_en
2004 apr 05 16 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. x = dont care. table 8 adc con?guration and dvi/hdcp registers (page 1); note 1 sync_dis 19h w - 000 0000 mdd_dvi_ on mdd_cs_ sog_en mdd_hs_ regen_on iif_dvi_on iif_cs_sog_ en iif_hs_ regen_on pll programming: 20h to 29h cd_pll_ctrl 20h w - 010 - 000 line_pll_ hs_pol line_pll_ vs_pol line_pll_en pll_src pll_pre_ div_en pll_en cd_pll_p_hi 21h w 00h pll_pre_div[15:8] cd_pll_p_lo 22h w 00h pll_pre_div[7:0] cd_pll_hi 23h w -- 00 0000 pll_m_div[1:0] pll_n_div[11:8] cd_pll_lo 24h w 00h pll_n_div[7:0] cd_lpll_hi 25h w -- 00 0000 line_pll_m_div[1:0] line_pll_n_div[11:8] cd_lpll_lo 26h w 00h line_pll_n_div[7:0] cd_lpll_pha 27h w --- 0 0000 line_pll_phase[4:0] cd_lpll_pd 28h w - 100 0000 phase_ auto phase_ select pd_pll_phase[4:0] cd_pll_lock 29h r ---- - xxx phase_ inlock pll_inlock llpll_inlock interface timing: 34h and 35h it_ctrl 34h w -- 01 1111 tmds_ select phase_ por_pol dvi_por_pol dvi_pon_ pol adc_pon_ pol bigger_ out_pol it_pll 35h w ---- 1111 pll_coast_ pol pll_pon_pol llpll_coast_ pol llpll_pon_ pol register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 adc programming: 00h to 06h adc_ctrl 00h w ---- - 000 sog_vs_ disable reserved sync_on_ green_en adc_r_bri 01h w 00h adc_red_brightness[7:0] adc_r_con 02h w 00h adc_red_contrast[7:0] adc_g_bri 03h w 00h adc_green_brightness[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 17 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. x = dont care. adc_g_con 04h w 00h adc_green_contrast[7:0] adc_b_bri 05h w 00h adc_blue_brightness[7:0] adc_b_con 06h w 00h adc_blue_contrast[7:0] hdcp: 80h to 97h dvi_hdcp_ctrl 80h w ---- -- 00 key_ decrypt_ enable hdcp_ enable dvi_hdcp_addr 81h w 74h hdcp_ddc_addr dvi_hdcp_kds_hi 82h w xx key_decrypt_seed[15:8] dvi_hdcp_kds_lo 83h w xx key_decrypt_seed[7:0] reserved 84h to 8ah dvi_hdcp_bksv4 8bh w xx hdcp_bksv[39:32] dvi_hdcp_bksv3 8ch w xx hdcp_bksv[31:24] dvi_hdcp_bksv2 8dh w xx hdcp_bksv[23:16] dvi_hdcp_bksv1 8eh w xx hdcp_bksv[15:8] dvi_hdcp_bksv0 8fh w xx hdcp_bksv[7:0] dvi_hdcp_kidx 90h w -- 00 0000 hdcp_key_index[5:0] dvi_hdcp_key6 91h w xx hdcp_key[55:48] dvi_hdcp_key5 92h w xx hdcp_key[47:40] dvi_hdcp_key4 93h w xx hdcp_key[39:32] dvi_hdcp_key3 94h w xx hdcp_key[31:24] dvi_hdcp_key2 95h w xx hdcp_key[23:16] dvi_hdcp_key1 96h w xx hdcp_key[15:8] dvi_hdcp_key0 97h w xx hdcp_key[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 18 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 9 mode detection con?guration registers (page 2); note 1 note 1. x = dont care. register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 mode detection: 00h to 0eh md_ctrl 00h w - 000 0000 no_vsync_ int_en clear_int int_lock delay_ vsync h_clocks_ accu h_clocks_ cont md_on md_int_en 01h w 0000 0000 jitter_int_en v_lines_ int_en v_clocks_ int_en h_clocks_ int_en no_hsync_ int_en vsync_int_ en vsync_pol_ int_en hsync_pol_ int_en md_pol 02h r --- 0 0011 jitter_ detected vsync_pol hsync_pol no_vsync no_hsync md_v_line_hi 03h r ---- - 000 v_lines[10:8] md_v_line_lo 04h r 00h v_lines[7:0] md_h_clk_hi 05h r 00h h_clocks[15:8] md_h_clk_lo 06h r 00h h_clocks[7:0] md_v_clk_hi 07h r 00h v_clocks[23:16] md_v_clk_md 08h r 00h v_clocks[15:8] md_v_clk_lo 09h r 00h v_clocks[7:0] md_int_hi 0ah r -- 00 0000 vsync_int jitter_int vsync_pol_ int hsync_pol_ int no_vsync_ int no_hsync_ int md_int_lo 0bh r ---- - 000 v_lines_int h_clocks_ int v_clocks_ int md_act_int 0ch r x000 0000 delock_int reserved dvs_act_int dhs_act_int asog_act_ int acsvs_act_ int avs_act_int ahs_act_int md_sync_act 0dh r -- 00 0000 dvs_active dhs_active asog_ active acsvs_ active avs_active ahs_active md_act_ien 0eh w 0000 0000 delock_int_ en reserved dvs_int_en dhs_int_en asog_int_ en acsvs_int_ en avs_int_en ahs_int_en dvi enhancements: 20h to 21h dvi_filter_0 20h w 00h dvi_?lter[7:0] recommended value fdh dvi_filter_1 21h w 00h dvi_?lter[7:0] recommended value 3fh
2004 apr 05 19 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 10 auto-adjustment con?guration registers (page 3); note 1 register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 auto-adjustment: 08h to 16h and 40h to 4dh aa_rc0_hi 08h w ---- - xxx ref_col_0[10:8] aa_rc0_lo 09h w xx ref_col_0[7:0] aa_rr0_hi 0ah w ---- xxxx ref_row_0[11:8] aa_rr0_lo 0bh w xx ref_row_0[7:0] aa_rc1_hi 0ch w ---- - xxx ref_col_1[10:8] aa_rc1_lo 0dh w xx ref_col_1[7:0] aa_rr1_hi 0eh w ---- xxxx ref_row_1[11:8] aa_rr1_lo 0fh w xx ref_row_1[7:0] aa_rcr0 10h w xx ref_colour_0[23:16] aa_rcg0 11h w xx ref_colour_0[15:8] aa_rcb0 12h w xx ref_colour_0[7:0] aa_rcr1 13h w xx ref_colour_1[23:16] aa_rcg1 14h w xx ref_colour_1[15:8] aa_rcb1 15h w xx ref_colour_1[7:0] aa_ctrl 16h w -- 01 1000 aa_cycles[1:0] aa_submode[1:0] aa_mode[1:0] aa_epr0 40h r 00h ref_pixel_red_0[7:0] aa_epg0 42h r 00h ref_pixel_green_0[7:0] aa_epb0 44h r 00h ref_pixel_blue_0[7:0] aa_epr1 41h r 00h ref_pixel_red_1[7:0] aa_epg1 43h r 00h ref_pixel_green_1[7:0] aa_epb1 45h r 00h ref_pixel_blue_1[7:0] aa_er0_hi 46h r 00h eval_row_0[15:8] aa_er0_lo 47h r 00h eval_row_0[7:0] aa_ec0_hi 48h r 00h eval_col_0[15:8] aa_ec0_lo 49h r 00h eval_col_0[7:0] aa_er1_hi 4ah r 00h eval_row_1[15:8] aa_er1_lo 4bh r 00h eval_row_1[7:0] aa_ec1_hi 4ch r 00h eval_col_1[15:8] aa_ec1_lo 4dh r 00h eval_col_1[7:0]
2004 apr 05 20 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. x = dont care. table 11 input interface con?guration registers (page 4) register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 input interface: 00h to 0fh ii_ctrl 00h w 0 - 00 0101 test_out_ en reverse_ ?eld_id interlace_ on test_pic_on ext_select dvi_select in_form_on ii_sync_ctrl 01h w 110 -- 011 sync_clk_ edge ext_clk_ edge dvi_de_ auto_adj hsync_ edge vs_pol hs_pol ii_adc_ctrl 02h w 1001 1111 delay_vs convert_2s dvi_use_ hsync dvi_de_pol gainc_en clamp_en gainc_pol clamp_pol ii_clamp_on 03h w 02h clamp_on_delay[7:0] ii_clamp_off 04h w 05h clamp_off_delay[7:0] ii_gainc_on 05h w 01h gainc_on_delay[7:0] ii_gainc_off 06h w 01h gainc_off_delay[7:0] ii_hlen_hi 07h w ---- 0000 in_h_length[11:8] ii_hlen_lo 08h w 3ch in_h_length[7:0] ii_vlen_hi 09h w ---- 0000 in_v_length[11:8] ii_vlen_lo 0ah w 28h in_v_length[7:0] ii_hoff_hi 0bh w ---- 0000 in_h_offset[11:8] ii_hoff_lo 0ch w 00h in_h_offset[7:0] ii_voff_hi 0dh w ---- 0000 in_v_offset[11:8] ii_voff_lo 0eh w 00h in_v_offset[7:0] ii_hjit 0fh w 05h hs_jitter_th[7:0] picture generator: 10h to 1ch pg_ctrl 10h w 0010 0010 invert white_ border h_ramp_r h_ramp_g h_ramp_b v_ramp_r v_ramp_g v_ramp_b pg_htotal_hi 11h w ---- 0000 h_length_total[11:8] pg_htotal_lo 12h w 51h h_length_total[7:0] pg_vtotal_hi 13h w ---- 0000 v_length_total[11:8] pg_vtotal_lo 14h w 35h v_length_total[7:0] pg_hstep1 15h w 01h h_step1[7:0] pg_hinc1 16h w 02h h_colour_inc1[7:0]
2004 apr 05 21 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 12 colour processing con?guration registers (page 5) table 13 decoupling fifo con?guration registers (page 6) pg_hstep2 17h w 00h h_step2[7:0] pg_hinc2 18h w ffh h_colour_inc2[7:0] pg_vstep1 19h w 14h v_step1[7:0] pg_vinc1 1ah w ffh v_colour_inc1[7:0] pg_vstep2 1bh w 01h v_step2[7:0] pg_vinc2 1ch w ffh v_colour_inc2[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 colour processing: 00h to 0bh cp_gain_y 00h w 80h gain_y[7:0] cp_gain_cb 01h w 80h gain_cb[7:0] cp_gain_cr 02h w 80h gain_cr[7:0] cp_offs_y 03h w 00h offset_y[7:0] cp_offs_cb 04h w 00h offset_cb[7:0] cp_offs_cr 05h w 00h offset_cr[7:0] cp_gain_r 06h w 80h gain_r[7:0] cp_gain_g 07h w 80h gain_g[7:0] cp_gain_b 08h w 80h gain_b[7:0] cp_offs_r 09h w 00h offset_r[7:0] cp_offs_g 0ah w 00h offset_g[7:0] cp_offs_b 0bh w 00h offset_b[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 decoupling fifo: 00h and 01h df_thld 00h w 01h ?fo_threshold[7:0] df_ctrl 01h w ---- -- 10 line_lock reserved register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 22 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 14 scaler con?guration registers (page 7); note 1 note 1. x = dont care. register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 upscaler: 00h to 09h, 0dh, 0fh, 11h and 14h to 18h usc_ctrl 00h w 1010 1101 ?lter_type[1:0] 1 0 0 0 usc_?ip_h usc_en usc_lut_adr 01h w 1100 0000 v_lut_sel h_lut_sel lut_addr[5:0] usc_lut_data 02h w xx lut_data[7:0] usc_h_inc_hi 03h w ---- 0000 h_scale_incr[11:8] usc_h_inc_lo 04h w 55h h_scale_incr[7:0] usc_h_corr 05h w - 010 0010 h_scale_corr[6:0] usc_v_inc_hi 06h w ---- 0000 v_scale_incr[11:8] usc_v_inc_lo 07h w 0110 0000 v_scale_incr[7:0] usc_v_corr 08h w - 000 0000 v_scale_corr[6:0] usc_h_pha 09h w -- 00 0000 h_phase_off[5:0] usc_v_pha_0 0dh w -- 00 0000 v_phase_off_0[5:0] usc_v_pha_1 0fh w -- 00 0000 v_phase_off_1[5:0] usc_pha_sel 11h w ---- - 000 v_phase_off_sel[1:0] set to 0 reserved 14h to 18h -- downscaler: 40h to 44h ds_en 40h w ---- -- 10 ?ip_h dsc_en ds_hsc 41h w - 011 0011 dsc_h_incr[6:0] ds_hsc_co 42h w - 001 0100 dsc_h_incr_corr[6:0] ds_vsc 43h w - 011 0000 dsc_v_incr[6:0] ds_vsc_co 44h w - 000 0000 dsc_v_incr_corr[6:0]
2004 apr 05 23 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 15 de?nition of osd con?guration registers (pages 8 and 9); note 1 register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 control registers (page 8) osd text : 00h to 1fh osdt_ctrl0 00h w x000 0000 area?ll_ start window_ shadow h_?ip v_?ip rotate_right zoom[1:0] text_on osdt_ctrl1 01h w ---- 0011 txt_ shadow_ style 011 osdt_bga 02h w 7fh bg_alpha[7:0] osdt_fga 03h w 7fh fg_alpha[7:0] osdt_wx 04h w 28h text_column[7:0] osdt_wy 05h w 1eh text_row[7:0] osdt_px_hi 06h w ---- - 000 x_position[10:8] osdt_px_lo 07h w 00h x_position[7:0] osdt_py_hi 08h w ---- - 000 y_position[10:8] osdt_py_lo 09h w 00h y_position[7:0] osdt_wshad 0ah w - 000 - 000 window_shadow_height[2:0] window_shadow_width[2:0] osdt_bdly 0bh w 3ch blink_delay[7:0] osdt_curx 0ch r/w 00h cursor_column[7:0] osdt_cury 0dh r/w 00h cursor_row[7:0] osdt_mask 0eh w 1111 1111 blink_mask shadow_ mask bg_mask fg_mask code_mask write_mode[2:0] osdt_prop2 0fh w - 000 0000 blink[1:0] shadow bg_trans fg_trans bg_alpha fg_alpha osdt_prop1 10h w 0001 1110 bg_colour[2:0] fg_colour[2:0]/palette[2:0] rom charcode [8] osdt_prop0 11h w 00h charcode[7:0] osdt_fr_x 12h w --- 0 1100 font_horizontal_resolution[4:0] osdt_fr_y 13h w --- 1 0010 font_vertical_resolution[4:0] osdt_sc_hi 14h w ---- --- 0 sc_ startcode [8] osdt_sc_lo 15h w 00h sc_startcode[7:0]
2004 apr 05 24 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osdt_cc_hi 16h w 0 --- --- 0 single_ char_def de?ne_ charcode [8] osdt_cc_lo 17h w 00h de?ne_charcode[7:0] osdt_cmask 18h w ffh de?nition_mask[7:0] osdt_cdef 19h w 00h char_de?nition[7:0] osdt_faulx 1ah w xx ?ll_area_upper_left_corner_x[7:0] osdt_fauly 1bh w xx ?ll_area_upper_left_corner_y[7:0] osdt_fabrx 1ch w xx ?ll_area_bottom_right_corner_x[7:0] osdt_fabry 1dh w xx ?ll_area_bottom_right_corner_y[7:0] osdt_slp1 1eh w 0001 0001 slider_border[3:0] slider_offset[3:0] osdt_slp0 1fh w --- 0 0001 slider_style slider_gap[3:0] osd bitmap : 20h to 31h osdb_ctrl0 20h w - 000 0000 bitmap_ behind h_?ip v_?ip rotate_right zoom[1:0] bitmap_on osdb_ctrl1 21h w - xx0 0011 bpp[1:0] bg_trans fg_trans 0 1 1 osdb_bga 22h w 7fh bg_alpha[7:0] osdb_fga 23h w 7fh fg_alpha[7:0] osdb_sx_hi 24h w ---- - 100 width[10:8] osdb_sx_lo 25h w 00h width[7:0] osdb_sy_hi 26h w ---- - 000 height[10:8] osdb_sy_lo 27h w 04h height[7:0] osdb_px_hi 28h w ---- - 000 x_position[10:8] osdb_px_lo 29h w 00h x_position[7:0] osdb_py_hi 2ah w ---- - 000 y_position[10:8] osdb_py_lo 2bh w 00h y_position[7:0] osdb_cx_hi 2ch w ---- - 000 cursor_column[10:8] osdb_cx_lo 2dh w 00h cursor_column[7:0] osdb_cy_hi 2eh w ---- - 000 cursor_row[10:8] osdb_cy_lo 2fh w 00h cursor_row[7:0] osdb_mask 30h w xx de?nition_mask[7:0] osdb_def 31h w xx pixel_de?nition[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 25 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osd pointer : 40h to 4ch osdp_ctrl0 40h w 0000 0000 autosel_en buffer_sel h_?ip v_?ip rotate_right zoom[1:0] pointer_on osdp_ctrl1 41h w -- 00 0011 anim_int_ en bg_trans fg_trans 0 1 1 osdp_bga 42h w ffh bg_alpha[7:0] osdp_fga 43h w ffh fg_alpha[7:0] osdp_ad 44h w 1eh anim_delay[7:0] osdp_dw 45h w ---- -- 00 defwidth[1:0] osdp_px_hi 46h w ---- - 000 x_position[10:8] osdp_px_lo 47h w 00h x_position[7:0] osdp_py_hi 48h w ---- - 000 y_position[10:8] osdp_py_lo 49h w 00h y_position[7:0] osdp_cx 4ah w --- 0 0000 cursor_column[4:0] osdp_cy 4bh w --- 0 0000 cursor_row[4:0] osdp_def 4ch w 00h pixel_de?nition[7:0] colour de?nitions (page 9) osd text colours : 00h to 92h osdt_fgc0r 00h w 00h osd_text_foreground_colour0_red[7:0] osdt_fgc0g 01h w 00h osd_text_foreground_colour0_green[7:0] osdt_fgc0b 02h w 00h osd_text_foreground_colour0_blue[7:0] osdt_fgc1r 03h w ffh osd_text_foreground_colour1_red[7:0] osdt_fgc1g 04h w 00h osd_text_foreground_colour1_green[7:0] osdt_fgc1b 05h w 00h osd_text_foreground_colour1_blue[7:0] osdt_fgc2r 06h w 00h osd_text_foreground_colour2_red[7:0] osdt_fgc2g 07h w ffh osd_text_foreground_colour2_green[7:0] osdt_fgc2b 08h w 00h osd_text_foreground_colour2_blue[7:0] osdt_fgc3r 09h w 00h osd_text_foreground_colour3_red[7:0] osdt_fgc3g 0ah w 00h osd_text_foreground_colour3_green[7:0] osdt_fgc3b 0bh w ffh osd_text_foreground_colour3_blue[7:0] osdt_fgc4r 0ch w ffh osd_text_foreground_colour4_red[7:0] osdt_fgc4g 0dh w ffh osd_text_foreground_colour4_green[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 26 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osdt_fgc4b 0eh w 00h osd_text_foreground_colour4_blue[7:0] osdt_fgc5r 0fh w 00h osd_text_foreground_colour5_red[7:0] osdt_fgc5g 10h w ffh osd_text_foreground_colour5_green[7:0] osdt_fgc5b 11h w ffh osd_text_foreground_colour5_blue[7:0] osdt_fgc6r 12h w ffh osd_text_foreground_colour6_red[7:0] osdt_fgc6g 13h w 00h osd_text_foreground_colour6_green[7:0] osdt_fgc6b 14h w ffh osd_text_foreground_colour6_blue[7:0] osdt_fgc7r 15h w ffh osd_text_foreground_colour7_red[7:0] osdt_fgc7g 16h w ffh osd_text_foreground_colour7_green[7:0] osdt_fgc7b 17h w ffh osd_text_foreground_colour7_blue[7:0] osdt_bgc0r 18h w 00h osd_text_background_colour0_red[7:0] osdt_bgc0g 19h w 00h osd_text_background_colour0_green[7:0] osdt_bgc0b 1ah w 00h osd_text_background_colour0_blue[7:0] osdt_bgc1r 1bh w ffh osd_text_background_colour1_red[7:0] osdt_bgc1g 1ch w 00h osd_text_background_colour1_green[7:0] osdt_bgc1b 1dh w 00h osd_text_background_colour1_blue[7:0] osdt_bgc2r 1eh w 00h osd_text_background_colour2_red[7:0] osdt_bgc2g 1fh w ffh osd_text_background_colour2_green[7:0] osdt_bgc2b 20h w 00h osd_text_background_colour2_blue[7:0] osdt_bgc3r 21h w 00h osd_text_background_colour3_red[7:0] osdt_bgc3g 22h w 00h osd_text_background_colour3_green[7:0] osdt_bgc3b 23h w ffh osd_text_background_colour3_blue[7:0] osdt_bgc4r 24h w ffh osd_text_background_colour4_red[7:0] osdt_bgc4g 25h w ffh osd_text_background_colour4_green[7:0] osdt_bgc4b 26h w 00h osd_text_background_colour4_blue[7:0] osdt_bgc5r 27h w 00h osd_text_background_colour5_red[7:0] osdt_bgc5g 28h w ffh osd_text_background_colour5_green[7:0] osdt_bgc5b 29h w ffh osd_text_background_colour5_blue[7:0] osdt_bgc6r 2ah w ffh osd_text_background_colour6_red[7:0] osdt_bgc6g 2bh w 00h osd_text_background_colour6_green[7:0] osdt_bgc6b 2ch w ffh osd_text_background_colour6_blue[7:0] osdt_bgc7r 2dh w ffh osd_text_background_colour7_red[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 27 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osdt_bgc7g 2eh w ffh osd_text_background_colour7_green[7:0] osdt_bgc7b 2fh w ffh osd_text_background_colour7_blue_7[7:0] osdt_p0c0r 30h w 00h osd_palette0_colour0_red[7:0] osdt_p0c0g 31h w 00h osd_palette0_colour0_green[7:0] osdt_p0c0b 32h w 00h osd_palette0_colour0_blue[7:0] osdt_p0c1r 33h w ffh osd_palette0_colour1_red[7:0] osdt_p0c1g 34h w 00h osd_palette0_colour1_green[7:0] osdt_p0c1b 35h w 00h osd_palette0_colour1_blue[7:0] osdt_p0c2r 36h w 00h osd_palette0_colour2_red[7:0] osdt_p0c2g 37h w ffh osd_palette0_colour2_green[7:0] osdt_p0c2b 38h w 00h osd_palette0_colour2_blue[7:0] osdt_p0c3r 39h w 00h osd_palette0_colour3_red[7:0] osdt_p0c3g 3ah w 00h osd_palette0_colour3_green[7:0] osdt_p0c3b 3bh w ffh osd_palette0_colour3_blue[7:0] osdt_p1c0r 3ch w ffh osd_palette1_colour0_red[7:0] osdt_p1c0g 3dh w ffh osd_palette1_colour0_green[7:0] osdt_p1c0b 3eh w 00h osd_palette1_colour0_blue[7:0] osdt_p1c1r 3fh w 00h osd_palette1_colour1_red[7:0] osdt_p1c1g 40h w ffh osd_palette1_colour1_green[7:0] osdt_p1c1b 41h w ffh osd_palette1_colour1_blue[7:0] osdt_p1c2r 42h w ffh osd_palette1_colour2_red[7:0] osdt_p1c2g 43h w 00h osd_palette1_colour2_green[7:0] osdt_p1c2b 44h w ffh osd_palette1_colour2_blue[7:0] osdt_p1c3r 45h w ffh osd_palette1_colour3_red[7:0] osdt_p1c3g 46h w ffh osd_palette1_colour3_green[7:0] osdt_p1c3b 47h w ffh osd_palette1_colour3_blue[7:0] osdt_p2c0r 48h w 40h osd_palette2_colour0_red[7:0] osdt_p2c0g 49h w 40h osd_palette2_colour0_green[7:0] osdt_p2c0b 4ah w 40h osd_palette2_colour0_blue[7:0] osdt_p2c1r 4bh w 80h osd_palette2_colour1_red[7:0] osdt_p2c1g 4ch w 00h osd_palette2_colour1_green[7:0] osdt_p2c1b 4dh w 00h osd_palette2_colour1_blue[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 28 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osdt_p2c2r 4eh w 00h osd_palette2_colour2_red[7:0] osdt_p2c2g 4fh w 80h osd_palette2_colour2_green[7:0] osdt_p2c2b 50h w 00h osd_palette2_colour2_blue[7:0] osdt_p2c3r 51h w 00h osd_palette2_colour3_red[7:0] osdt_p2c3g 52h w 00h osd_palette2_colour3_green[7:0] osdt_p2c3b 53h w 80h osd_palette2_colour3_blue[7:0] osdt_p3c0r 54h w 80h osd_palette3_colour0_red[7:0] osdt_p3c0g 55h w 80h osd_palette3_colour0_green[7:0] osdt_p3c0b 56h w 00h osd_palette3_colour0_blue[7:0] osdt_p3c1r 57h w 00h osd_palette3_colour1_red[7:0] osdt_p3c1g 58h w 80h osd_palette3_colour1_green[7:0] osdt_p3c1b 59h w 80h osd_palette3_colour1_blue[7:0] osdt_p3c2r 5ah w 80h osd_palette3_colour2_red[7:0] osdt_p3c2g 5bh w 00h osd_palette3_colour2_green[7:0] osdt_p3c2b 5ch w 80h osd_palette3_colour2_blue[7:0] osdt_p3c3r 5dh w 80h osd_palette3_colour3_red[7:0] osdt_p3c3g 5eh w 80h osd_palette3_colour3_green[7:0] osdt_p3c3b 5fh w 80h osd_palette3_colour3_blue[7:0] osdt_p4c0r 60h w 00h osd_palette4_colour0_red[7:0] osdt_p4c0g 61h w 00h osd_palette4_colour0_green[7:0] osdt_p4c0b 62h w 00h osd_palette4_colour0_blue[7:0] osdt_p4c1r 63h w 3fh osd_palette4_colour1_red[7:0] osdt_p4c1g 64h w 3fh osd_palette4_colour1_green[7:0] osdt_p4c1b 65h w 3fh osd_palette4_colour1_blue[7:0] osdt_p4c2r 66h w 7fh osd_palette4_colour2_red[7:0] osdt_p4c2g 67h w 7fh osd_palette4_colour2_green[7:0] osdt_p4c2b 68h w 7fh osd_palette4_colour2_blue[7:0] osdt_p4c3r 69h w ffh osd_palette4_colour3_red[7:0] osdt_p4c3g 6ah w ffh osd_palette4_colour3_green[7:0] osdt_p4c3b 6bh w ffh osd_palette4_colour3_blue[7:0] osdt_p5c0r 6ch w 00h osd_palette5_colour0_red[7:0] osdt_p5c0g 6dh w 00h osd_palette5_colour0_green[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 29 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osdt_p5c0b 6eh w 00h osd_palette5_colour0_blue[7:0] osdt_p5c1r 6fh w 7fh osd_palette5_colour1_red[7:0] osdt_p5c1g 70h w 00h osd_palette5_colour1_green[7:0] osdt_p5c1b 71h w 00h osd_palette5_colour1_blue[7:0] osdt_p5c2r 72h w 00h osd_palette5_colour2_red[7:0] osdt_p5c2g 73h w 7fh osd_palette5_colour2_green[7:0] osdt_p5c2b 74h w 00h osd_palette5_colour2_blue[7:0] osdt_p5c3r 75h w 00h osd_palette5_colour3_red[7:0] osdt_p5c3g 76h w 00h osd_palette5_colour3_green[7:0] osdt_p5c3b 77h w 7fh osd_palette5_colour3_blue[7:0] osdt_p6c0r 78h w c0h osd_palette6_colour0_red[7:0] osdt_p6c0g 79h w c0h osd_palette6_colour0_green[7:0] osdt_p6c0b 7ah w c0h osd_palette6_colour0_blue[7:0] osdt_p6c1r 7bh w 80h osd_palette6_colour1_red[7:0] osdt_p6c1g 7ch w 80h osd_palette6_colour1_green[7:0] osdt_p6c1b 7dh w 80h osd_palette6_colour1_blue[7:0] osdt_p6c2r 7eh w e0h osd_palette6_colour2_red[7:0] osdt_p6c2g 7fh w e0h osd_palette6_colour2_green[7:0] osdt_p6c2b 80h w e0h osd_palette6_colour2_blue[7:0] osdt_p6c3r 81h w 00h osd_palette6_colour3_red[7:0] osdt_p6c3g 82h w 00h osd_palette6_colour3_green[7:0] osdt_p6c3b 83h w 00h osd_palette6_colour3_blue[7:0] osdt_p7c0r 84h w c0h osd_palette7_colour0_red[7:0] osdt_p7c0g 85h w c0h osd_palette7_colour0_green[7:0] osdt_p7c0b 86h w c0h osd_palette7_colour0_blue[7:0] osdt_p7c1r 87h w e0h osd_palette7_colour1_red[7:0] osdt_p7c1g 88h w e0h osd_palette7_colour1_green[7:0] osdt_p7c1b 89h w e0h osd_palette7_colour1_blue[7:0] osdt_p7c2r 8ah w 80h osd_palette7_colour2_red[7:0] osdt_p7c2g 8bh w 80h osd_palette7_colour2_green[7:0] osdt_p7c2b 8ch w 80h osd_palette7_colour2_blue[7:0] osdt_p7c3r 8dh w 00h osd_palette7_colour3_red[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 30 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osdt_p7c3g 8eh w 00h osd_palette7_colour3_green[7:0] osdt_p7c3b 8fh w 00h osd_palette7_colour3_blue[7:0] osdt_scr 90h w 00h osd_shadow_colour_red[7:0] osdt_scg 91h w 00h osd_shadow_colour_green[7:0] osdt_scb 92h w 00h osd_shadow_colour_blue[7:0] osd bitmap colours : 93h to c2 osdb_c0r 93h w 00h osd_bitmap_colour0_red[7:0] osdb_c0g 94h w 00h osd_bitmap_colour0_green[7:0] osdb_c0b 95h w 00h osd_bitmap_colour0_blue[7:0] osdb_c1r 96h w ffh osd_bitmap_colour1_red[7:0] osdb_c1g 97h w 00h osd_bitmap_colour1_green[7:0] osdb_c1b 98h w 00h osd_bitmap_colour1_blue[7:0] osdb_c2r 99h w 00h osd_bitmap_colour2_red[7:0] osdb_c2g 9ah w ffh osd_bitmap_colour2_green[7:0] osdb_c2b 9bh w 00h osd_bitmap_colour2_blue[7:0] osdb_c3r 9ch w 00h osd_bitmap_colour3_red[7:0] osdb_c3g 9dh w 00h osd_bitmap_colour3_green[7:0] osdb_c3b 9eh w ffh osd_bitmap_colour3_blue[7:0] osdb_c4r 9fh w ffh osd_bitmap_colour4_red[7:0] osdb_c4g a0h w ffh osd_bitmap_colour4_green[7:0] osdb_c4b a1h w 00h osd_bitmap_colour4_blue[7:0] osdb_c5r a2h w 00h osd_bitmap_colour5_red[7:0] osdb_c5g a3h w ffh osd_bitmap_colour5_green[7:0] osdb_c5b a4h w ffh osd_bitmap_colour5_blue[7:0] osdb_c6r a5h w ffh osd_bitmap_colour6_red[7:0] osdb_c6g a6h w 00h osd_bitmap_colour6_green[7:0] osdb_c6b a7h w ffh osd_bitmap_colour6_blue[7:0] osdb_c7r a8h w ffh osd_bitmap_colour7_red[7:0] osdb_c7g a9h w ffh osd_bitmap_colour7_green[7:0] osdb_c7b aah w ffh osd_bitmap_colour7_blue[7:0] osdb_c8r abh w 40h osd_bitmap_colour8_red[7:0] osdb_c8g ach w 40h osd_bitmap_colour8_green[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 31 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... osdb_c8b adh w 40h osd_bitmap_colour8_blue[7:0] osdb_c9r aeh w 80h osd_bitmap_colour9_red[7:0] osdb_c9g afh w 00h osd_bitmap_colour9_green[7:0] osdb_c9b b0h w 00h osd_bitmap_colour9_blue[7:0] osdb_c10r b1h w 00h osd_bitmap_colour10_red[7:0] osdb_c10g b2h w 80h osd_bitmap_colour10_green[7:0] osdb_c10b b3h w 00h osd_bitmap_colour10_blue[7:0] osdb_c11r b4h w 00h osd_bitmap_colour11_red[7:0] osdb_c11g b5h w 00h osd_bitmap_colour11_green[7:0] osdb_c11b b6h w 80h osd_bitmap_colour11_blue[7:0] osdb_c12r b7h w 80h osd_bitmap_colour12_red[7:0] osdb_c12g b8h w 80h osd_bitmap_colour12_green[7:0] osdb_c12b b9h w 00h osd_bitmap_colour12_blue[7:0] osdb_c13r bah w 00h osd_bitmap_colour13_red[7:0] osdb_c13g bbh w 80h osd_bitmap_colour13_green[7:0] osdb_c13b bch w 80h osd_bitmap_colour13_blue[7:0] osdb_c14r bdh w 80h osd_bitmap_colour14_red[7:0] osdb_c14g beh w 00h osd_bitmap_colour14_green[7:0] osdb_c14b bfh w 80h osd_bitmap_colour14_blue[7:0] osdb_c15r c0h w 80h osd_bitmap_colour15_red[7:0] osdb_c15g c1h w 80h osd_bitmap_colour15_green[7:0] osdb_c15b c2h w 80h osd_bitmap_colour15_blue[7:0] osd pointer colours : c3h to ceh osdp_c0r c3h w 00h osd_pointer_colour0_red[7:0] osdp_c0g c4h w 00h osd_pointer_colour0_green[7:0] osdp_c0b c5h w 00h osd_pointer_colour0_blue[7:0] osdp_c1r c6h w ffh osd_pointer_colour1_red[7:0] osdp_c1g c7h w 00h osd_pointer_colour1_green[7:0] osdp_c1b c8h w 00h osd_pointer_colour1_blue[7:0] osdp_c2r c9h w 00h osd_pointer_colour2_red[7:0] osdp_c2g cah w ffh osd_pointer_colour2_green[7:0] osdp_c2b cbh w 00h osd_pointer_colour2_blue[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 32 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. x = dont care. table 16 colour look-up table and dithering con?guration registers (page 10) table 17 output interface con?guration registers (page 11); note 1 osdp_c3r cch w 00h osd_pointer_colour3_red[7:0] osdp_c3g cdh w 00h osd_pointer_colour3_green[7:0] osdp_c3b ceh w ffh osd_pointer_colour3_blue[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 colour look-up table: 00h to 03h cl_ctrl 00h w -- 00 0000 write_ hsynced quick_prog red_prog green_prog blue_prog cc_on cl_index 01h w 00h colour_index[7:0] cl_value_hi 02h w ---- -- 00 colour_value[9:8] cl_value_lo 03h w 00h colour_value[7:0] temporal dithering: 80h to 83h dt_ctrl 80h w 1 --- 1 --- dither_ bypass dither_out_ bits dt_colmap 81h w 11 -- ---- dither_colmap[1:0] dt_mode 82h w 00 -- - 100 dither_ rand_mode dither_ rand_mono dither_idx_ofs_reg[2:0] dt_noise 83h w 0 --- -- 0 - dither_ add_noise dither_ noise_mag register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0 output interface: 01h to 39h, 40h to 4ah, 51h to 59h, 61h to 6ah, 71h to 7ah, 81h to 8ah, 91h to 9ah, a1h to aah, b1h to bah, c1h to cah, d1h to deh, e1h to eeh and f0h to f7h oi_wx_hi 01h w ---- - 000 wait_column[10:8] oi_wx_lo 02h w 02h wait_column[7:0] oi_inva_del 03h w 0000 0000 pin_drv_inva[2:0] inversion_a_pin_delay[4:0] oi_invb_del 04h w 0000 0000 pin_drv_invb[2:0] inversion_b_pin_delay[4:0] oi_psx_hi 05h w ---- - 000 picture_start_x[10:8] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 33 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... oi_psx_lo 06h w 09h picture_start_x[7:0] oi_psy_hi 07h w ---- - 000 picture_start_y[10:8] oi_psy_lo 08h w 07h picture_start_y[7:0] oi_asx_hi 09h w ---- - 000 active_start_x[10:8] oi_asx_lo 0ah w 07h active_start_x[7:0] oi_asy_hi 0bh w ---- - 000 active_start_y[10:8] oi_asy_lo 0ch w 05h active_start_y[7:0] oi_pex_hi 0dh w ---- - 000 picture_end_x[10:8] oi_pex_lo 0eh w 54h picture_end_x[7:0] oi_pey_hi 0fh w ---- - 000 picture_end_y[10:8] oi_pey_lo 10h w 3eh picture_end_y[7:0] oi_aex_hi 11h w ---- - 000 active_end_x[10:8] oi_aex_lo 12h w 56h active_end_x[7:0] oi_aey_hi 13h w ---- - 000 active_end_y[10:8] oi_aey_lo 14h w 40h active_end_y[7:0] oi_fy_hi 15h w ---- - 000 last_line[10:8] oi_fy_lo 16h w 46h last_line[7:0] oi_fx_hi 17h w ---- - 000 blank_line_length[10:8] oi_fx_lo 18h w 5eh blank_line_length[7:0] oi_alx_hi 19h w ---- - 000 active_line_length[10:8] oi_alx_lo 1ah w 5ch active_line_length[7:0] oi_px_hi 1bh w ---- - 000 picture_line_length[10:8] oi_px_lo 1ch w 5ah picture_line_length[7:0] oi_wm 1dh w ---- -- 01 wait_mode[1:0] oi_b0r 1eh w -- 00 0011 msb_align swap inv port_a_conf[2:0] oi_b0g 1fh w -- 00 0001 msb_align swap inv port_b_conf[2:0] oi_b0b 20h w -- 00 0000 msb_align swap inv port_c_conf[2:0] oi_b1r 21h w -- 00 0111 msb_align swap inv port_d_conf[2:0] oi_b1g 22h w -- 00 0101 msb_align swap inv port_e_conf[2:0] oi_b1b 23h w -- 00 0100 msb_align swap inv port_f_conf[2:0] oi_pad 24h w 0000 0000 pin_drv_pa[2:0] pin_delay[4:0] oi_pbd 25h w 0000 0000 pin_drv_pb[2:0] pin_delay[4:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 34 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... oi_pcd 26h w 0000 0000 pin_drv_pc[2:0] pin_delay[4:0] oi_pdd 27h w 0000 0000 pin_drv_pd[2:0] pin_delay[4:0] oi_ped 28h w 0000 0000 pin_drv_pe[2:0] pin_delay[4:0] oi_pfd 29h w 0000 0000 pin_drv_pf[2:0] pin_delay[4:0] oi_ctrl0 2ah w - 10 - 0100 ivsl1 ivsl0 0 oi_enable power_ down blank_ mode oi_ctrl1 2bh w - 000 0000 pclk_pin_delay[4:0] double_ pixel pclk_pol oi_boc_r 2ch w 00h border_colour_red[7:0] oi_boc_g 2dh w ffh border_colour_green[7:0] oi_boc_b 2eh w 00h border_colour_blue[7:0] oi_blc_r 2fh w ffh blank_colour_red[7:0] oi_blc_g 30h w 00h blank_colour_green[7:0] oi_blc_b 31h w 00h blank_colour_blue[7:0] oi_g0asx_hi 32h w ---- - 000 point1_x[10:8] oi_g0asx_lo 33h w 01h point1_x[7:0] oi_g0asy_hi 34h w ---- - 000 point1_y[10:8] oi_g0asy_lo 35h w 01h point1_y[7:0] oi_g0aex_hi 36h w ---- - 000 point2_x[10:8] oi_g0aex_lo 37h w 25h point2_x[7:0] oi_g0aey_hi 38h w ---- - 000 point2_y[10:8] oi_g0aey_lo 39h w 02h point2_y[7:0] oi_g0ac 40h w ---- 0100 pol_csg 0a+0b frame/line point2_ tog/reset point1_ tog/set oi_g0bsx_hi 41h w ---- - 000 point1_x[10:8] oi_g0bsx_lo 42h w 00h point1_x[7:0] oi_g0bsy_hi 43h w ---- - 000 point1_y[10:8] oi_g0bsy_lo 44h w 00h point1_y[7:0] oi_g0bex_hi 45h w ---- - 000 point2_x[10:8] oi_g0bex_lo 46h w 00h point2_x[7:0] oi_g0bey_hi 47h w ---- - 000 point2_y[10:8] oi_g0bey_lo 48h w 00h point2_y[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 35 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... oi_g0bc 49h w ---- - 000 frame/line point2_ tog/reset point1_ tog/set oi_g0bd 4ah w x000 0000 pin_drv_csg0[2:0] pin_delay[4:0] oi_g1asx_hi 51h w ---- - 000 point1_x[10:8] oi_g1asx_lo 52h w 03h point1_x[7:0] oi_g1asy_hi 53h w ---- - 000 point1_y[10:8] oi_g1asy_lo 54h w 01h point1_y[7:0] oi_g1aex_hi 55h w ---- - 000 point2_x[10:8] oi_g1aex_lo 56h w 05h point2_x[7:0] oi_g1aey_hi 57h w ---- - 000 point2_y[10:8] oi_g1aey_lo 58h w 46h point2_y[7:0] oi_g1ac 59h w ---- 0000 pol_csg 1a+1b frame/line point2_ tog/reset point1_ tog/set oi_g1bsx_hi 61h w ---- - 000 point1_x[10:8] oi_g1bsx_lo 62h w 00h point1_x[7:0] oi_g1bsy_hi 63h w ---- - 000 point1_y[10:8] oi_g1bsy_lo 64h w 00h point1_y[7:0] oi_g1bex_hi 65h w ---- - 000 point2_x[10:8] oi_g1bex_lo 66h w 00h point2_x[7:0] oi_g1bey_hi 67h w ---- - 000 point2_y[10:8] oi_g1bey_lo 68h w 00h point2_y[7:0] oi_g1bc 69h w ---- - 000 frame/line point2_ tog/reset point1_ tog/set oi_g1bd 6ah w x000 0000 pin_drv_csg1[2:0] pin_delay[4:0] oi_g2sx_hi 71h w ---- - 000 point1_x[10:8] oi_g2sx_lo 72h w 06h point1_x[7:0] oi_g2sy_hi 73h w ---- - 000 point1_y[10:8] oi_g2sy_lo 74h w 05h point1_y[7:0] oi_g2ex_hi 75h w ---- - 000 point2_x[10:8] oi_g2ex_lo 76h w 56h point2_x[7:0] oi_g2ey_hi 77h w ---- - 000 point2_y[10:8] oi_g2ey_lo 78h w 40h point2_y[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 36 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... oi_g2c 79h w --- 0 1000 invol_ csg3 pol frame/line point2_ tog/reset point1_ tog/set oi_g2d 7ah w x000 0000 pin_drv_csg2[2:0] pin_delay[4:0] oi_g3sx_hi 81h w ---- - 000 point1_x[10:8] oi_g3sx_lo 82h w 00h point1_x[7:0] oi_g3sy_hi 83h w ---- - 000 point1_y[10:8] oi_g3sy_lo 84h w 00h point1_y[7:0] oi_g3ex_hi 85h w ---- - 000 point2_x[10:8] oi_g3ex_lo 86h w 00h point2_x[7:0] oi_g3ey_hi 87h w ---- - 000 point2_y[10:8] oi_g3ey_lo 88h w 00h point2_y[7:0] oi_g3c 89h w ---- 0000 pol frame/line point2_ tog/reset point1_ tog/set oi_g3d 8ah w x000 0000 pin_drv_csg3[2:0] pin_delay[4:0] oi_g4sx_hi 91h w ---- - 000 point1_x[10:8] oi_g4sx_lo 92h w 00h point1_x[7:0] oi_g4sy_hi 93h w ---- - 000 point1_y[10:8] oi_g4sy_lo 94h w 00h point1_y[7:0] oi_g4ex_hi 95h w ---- - 000 point2_x[10:8] oi_g4ex_lo 96h w 00h point2_x[7:0] oi_g4ey_hi 97h w ---- - 000 point2_y[10:8] oi_g4ey_lo 98h w 00h point2_y[7:0] oi_g4c 99h w --- 0 0000 invol_ csg5 pol frame/line point2_ tog/reset point1_ tog/set oi_g4d 9ah w x000 0000 pin_drv_csg4[2:0] pin_delay[4:0] oi_g5sx_hi a1h w ---- - 000 point1_x[10:8] oi_g5sx_lo a2h w 00h point1_x[7:0] oi_g5sy_hi a3h w ---- - 000 point1_y[10:8] oi_g5sy_lo a4h w 00h point1_y[7:0] oi_g5ex_hi a5h w ---- - 000 point2_x[10:8] oi_g5ex_lo a6h w 00h point2_x[7:0] oi_g5ey_hi a7h w ---- - 000 point2_y[10:8] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 37 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... oi_g5ey_lo a8h w 00h point2_y[7:0] oi_g5c a9h w ---- 0000 pol frame/line point2_ tog/reset point1_ tog/set oi_g5d aah w x000 0000 pin_drv_csg5[2:0] pin_delay[4:0] oi_g6sx_hi b1h w ---- - 000 point1_x[10:8] oi_g6sx_lo b2h w 00h point1_x[7:0] oi_g6sy_hi b3h w ---- - 000 point1_y[10:8] oi_g6sy_lo b4h w 00h point1_y[7:0] oi_g6ex_hi b5h w ---- - 000 point2_x[10:8] oi_g6ex_lo b6h w 00h point2_x[7:0] oi_g6ey_hi b7h w ---- - 000 point2_y[10:8] oi_g6ey_lo b8h w 00h point2_y[7:0] oi_g6c b9h w ---- 0000 pol frame/line point2_ tog/reset point1_ tog/set oi_g6d bah w x000 0000 pin_drv_csg6[2:0] pin_delay[4:0] oi_g7sx_hi c1h w ---- - 000 point1_x[10:8] oi_g7sx_lo c2h w 00h point1_x[7:0] oi_g7sy_hi c3h w ---- - 000 point1_y[10:8] oi_g7sy_lo c4h w 00h point1_y[7:0] oi_g7ex_hi c5h w ---- - 000 point2_x[10:8] oi_g7ex_lo c6h w 00h point2_x[7:0] oi_g7ey_hi c7h w ---- - 000 point2_y[10:8] oi_g7ey_lo c8h w 00h point2_y[7:0] oi_g7c c9h w ---- 0000 pol frame/line point2_ tog/reset point1_ tog/set oi_g7d cah w x000 0000 pin_drv_csg7[2:0] pin_delay[4:0] oi_g8sx_hi d1h w ---- - 000 point1_x[10:8] oi_g8sx_lo d2h w 00h point1_x[7:0] oi_g8sy_hi d3h w ---- - 000 point1_y[10:8] oi_g8sy_lo d4h w 00h point1_y[7:0] oi_g8ex_hi d5h w ---- - 000 point2_x[10:8] oi_g8ex_lo d6h w 00h point2_x[7:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 38 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... oi_g8ey_hi d7h w ---- - 000 point2_y[10:8] oi_g8ey_lo d8h w 00h point2_y[7:0] oi_g8c d9h w 0000 0000 skip_mode point3_ toggle point3_ on/off point3_ frm/line pol frame/line point2_ tog/reset point1_ tog/set oi_g8d dah w x000 0000 pin_drv_csg8[2:0] pin_delay[4:0] oi_g8spx_hi dbh w ---- - 000 point3_x[10:8] oi_g8spx_lo dch w 00h point3_x[7:0] oi_g8spy_hi ddh w ---- - 000 point3_y[10:8] oi_g8spy_lo deh w 00h point3_y[7:0] oi_g9sx_hi e1h w ---- - 000 point1_x[10:8] oi_g9sx_lo e2h w 00h point1_x[7:0] oi_g9sy_hi e3h w ---- - 000 point1_y[10:8] oi_g9sy_lo e4h w 00h point1_y[7:0] oi_g9ex_hi e5h w ---- - 000 point2_x[10:8] oi_g9ex_lo e6h w 00h point2_x[7:0] oi_g9ey_hi e7h w ---- - 000 point2_y[10:8] oi_g9ey_lo e8h w 00h point2_y[7:0] oi_g9c e9h w 0000 0000 skip_mode point3_ toggle point3_ on/off point3_ frm/line pol frame/line point2_ tog/reset point1_ tog/set oi_g9d eah w x000 0000 pin_drv_csg9[2:0] pin_delay[4:0] oi_g9spx_hi ebh w ---- - 000 point3_x[10:8] oi_g9spx_lo ech w 00h point3_x[7:0] oi_g9spy_hi edh w ---- - 000 point3_y[10:8] oi_g9spy_lo eeh w 00h point3_y[7:0] oi_pwm0 f0h w 00h pwm[7:0] oi_pwm1 f1h w --- x x000 pwm_hs_ sync pwm_pol pwm_div[2:0] oi_fcr f2h w 00h frame_col[23:16] oi_fcg f3h w 00h frame_col[15:8] oi_fcb f4h w ffh frame_col[7:0] oi_fc_en f5h w ---- --- 0 enable_ frame_ generator register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 39 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... note 1. x = dont care. oi_pwmd f6h w 000 - ---- pin_drv_pwm[2:0] oi_wc f6h r 00h wait_count[7:0] oi_pclkd f7h w 0000 00 -- pin_drv_pclk[2:0] pin_drv_outen[2:0] register adr r/w reset d7 d6 d5 d4 d3 d2 d1 d0
2004 apr 05 40 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.2 device id the readable parameter device_id contains the ic version code. the current version returns the code 131ch. 7.3 initialization the external power-on reset is active low and applied to pin rst. front-end, back-end and the output interface can be switched into the reset state individually by the i 2 c-bus programming using reset_fclk, reset_bclk, reset_oif and reset_dviclk at register gc_reset (fch). each domain reset is active if the corresponding programming bit is set to logic 1. 7.4 clock management all clock management configuration registers are mapped to register page 0. a block diagram of the clock distribution is given in fig.5. the clock source for the decoupling fifo is selected by fifo_fclk. if fifo_fclk is set to logic 1, the front-end clock is applied to the decoupling fifo; otherwise the back-end clock is used. the decoupling fifo always has to be supplied with the clock signal of the higher clock rate. handbook, full pagewidth mhc213 hs_pll vclk (i/o) adc sample clock front-end clock vclk_in_en dvi_select vclk_in_en line_pll_phase [ 4:0 ] back-end clock system clock configuration clock vs_pll dvi clock clk bclk_in_en line-locked pll configuration signals phase shift ? 4 panel clock pll configuration signals 0 1 0 1 frontend_bclk 0 1 clk_div4 0 1 0 1 ? 2 cfgclk_select 0 1 fig.5 clock distribution.
2004 apr 05 41 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.4.1 c lock signals 7.4.1.1 system clock the system clock is applied to pin clk and is used to drive the internal control structures and block configuration, and serves as input for the panel clock pll. the maximum clock rate is 50 mhz. the system clock is directly taken from pin clk if clk_div4 is set to logic 0; otherwise the system clock is derived from the clock signal at pin clk additionally divided by 4 as shown in table 18. table 18 system clock switching modes 7.4.1.2 back-end clock the back-end clock is the pixel clock used in data processing behind the decoupling fifo. possible clock rates lie between 5 and 100 mhz in case of single pixel panel output, but it is identical with the panel clock; if using double pixel mode it equals twice the panel clock. the clock signal is generated by the panel clock pll based on the system clock if bclk_in_en is set to logic 0; otherwise the signal applied externally to pin clk is used as system clock (see table 19). table 19 back-end clock switching modes 7.4.1.3 front-end clock the front-end clock is the pixel clock of the input section and is generated by the line pll in case of analog rgb input or provided by the dvi data stream in case of dvi input. the front-end clock rate can be up to 110 mhz. either the dvi clock or the line pll generated clock signal (for analog input) is used depending on the selected video source. in both cases pin vclk is switched as output for the used clock signal. an externally generated clock signal can also be connected to pin vclk if vclk_in_en is set to logic 1. alternatively, the back-end clock can be selected as front-end clock, which is particularly needed if the picture generator is used without an external clock source. front-end clock modes are shown in table 20. table 20 front-end clock switching modes; note 1 note 1. x = dont care. 7.4.1.4 con?guration clock the internal configuration clock is driving the configuration parameters section of all modules. it is usually running at half the back-end clock frequency. if somehow the back-end clock is not usable for the configuration, the system clock could be used to drive the configuration clock instead. the selection of the configuration clock source could either be done automatically monitoring the back-end clock or forced manually if this is desired. for power saving issues the configuration clock is powered-down during inactive periods when no data is received or requested via the i 2 c-bus interface. see table 21 for configuration clock switching options. table 21 con?guration clock switching modes clk_div4 system clock description 0 clk direct input 1 1 4 clk divided by 4 bclk_in_en back-end clock description 1 clk external clock 0 pll clock internal clock generation frontend _bclk dvi_ select vclk _in_ en front-end clock description 1 x x back-end clock initialization 0 1 x dvi clock dvi input 0 0 1 vclk external clock generation 0 0 0 line pll clock internal clock generation cfgclk_select configuration clock description 0 half back-end clock application (stable back-end clock) 1 clk initialization
2004 apr 05 42 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.4.2 c lock activation control the clock signals of auto-adjustment, downscaler, upscaler and osd module are powered-down automatically during inactivity if programming bits aaclk_auto, dscclk_auto, uscclk_auto and osdclk_auto respectively in register cd_clk_auto (11h) are set to logic 1. otherwise the clock signals are switched on and off according to the state of bits aaclk_on, dscclk_on, uscclk_on and osdclk_on respectively in register cd_clk_en (10h). the general configuration and the osd configuration clock signal are also powered-down during inactivity unless forced active, when cfgclk_on or osd_cfgclk_on respectively (cd_clk_en, 10h) is set to logic 1. when automatic activation is selected, each clock signal is active during either power-on or the programmable reset of the specific domain and whenever the concerned module is activated. 7.4.3 pll programming the saa6713h contains two plls: line-locked pll generating the sample clock from the hsync signal (see fig.6) pll running on the system clock generating the panel clock (see fig.7). the pll programming registers are mapped to register page 0. the plls are activated by pll_en and line_pll_en and the back-end clock pll pre-divider by pll_pre_div_en at register cd_pll_ctrl (20h). bits line_pll_vs_pol and line_pll_hs_pol define the polarity of the vertical and horizontal sync inputs. each bit has to be set to logic 1 in case of positive (active high) polarity of the corresponding sync signal; otherwise to logic 0. the outputs for the pre-divider, n-divider and m-divider ratios are set accordingly to bits pll_pre_div, pll_m_div, pll_n_div, line_pll_m_div and line_pll_n_div at registers cd_pll_p_hi to cd_lpll_lo (21h to 26h). the pll_n_div is a programmable divider between 100 to 4096. the relation between hsync and pll_clk is: pll_clk = pll_n_div hsync. the frequency of the oscillator should be selected at minimum two times pll_clk. the pll_m_div is a programmable divider between 00 = 1, 01 = 2, 10 = 2, 11 = 4 and limits the current controlled oscillator tuning range. the line pll clock is finally phase shifted as defined in steps of 11.25 degrees by line_pll_phase at register cd_lpll_pha (27h). for the auto-adjustment phase distortion measurement register cd_lpll_pd contains an alternative phase value pd_pll_phase for the line pll. parameter phase_auto enables switching between both phase values controlled by the auto-adjustment if set to logic 1, or manual selection by phase_select. handbook, full pagewidth mhc215 ? 2 line pll clock frequency and phase detector oscillator 50 to 320 mhz line_pll_en m-divider line_pll_m_div [ 1:0 ] n-divider line_pll_n_div [ 11:0 ] hs_pll line_vs_pol vs_pll line_hs_pol fig.6 line pll block diagram.
2004 apr 05 43 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc214 ? 2 clk pll clock pre-divider pll_pre_div_en pll_pre_div [ 15:0 ] frequency and phase detector oscillator 50 to 320 mhz pll_en m-divider pll_m_div [ 1:0 ] n-divider pll_n_div [ 11:0 ] fig.7 pll block diagram. 7.5 synchronization pulse distribution the line-locked pll, input interface and mode detection are provided with horizontal and vertical synchronization pulse signals (hsync and vsync). signal switching is controlled by configuration registers sync_sel (18h at page 0) and sync_dis (19h at page 0). a composite sync decoder and hsync regeneration can be inserted. possible selections and the concerned configuration parameters are shown in fig.8 and described more detailed in the sections 7.5.1 to 7.5.5. 7.5.1 c omposite sync input the composite sync decoder input is selected by cs_dvi_de and sog_en. this allows to input the separated sog provided by the sync-on-green slicer, a composite sync applied at input pin hsync or data enable dvi_de decoded from the dvi stream (see table 22). the sync-on-green slicer has to be enabled by setting sync_on_green_en in register adc_ctrl (00h at page 1) to logic 1. to provide a stable hsync during the vsync, the sync-on-green slicer might have to be disabled during the vsync which is performed automatically if sog_vs_disable is set to logic 1; otherwise the sync-on-green slicer is constantly enabled. the composite sync decoder will regenerate hsync and vsync signals for internal use. figure 9 shows the composite sync modes that can be used. the maximum number of equalizing pulses (csync-3 and csync-4) may not exceed 30. table 22 composite sync decoder input selection; note 1 note 1. x = dont care. cs_dvi_en sog_en csync 1 x dvi_de 0 1 sog 0 0 hsync
2004 apr 05 44 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc216 hs_dvi hs_iif hs_pll vs_mdd vsync vs_dvi vsync vs_dvi vs_iif vs_pll hs_mdd hs_regen_in_en iif_hs_regen_on mdd_hs_regen_on iif_cs_sog_en iif_cs_sog_en mdd_dvi_on mdd_cs_sog_en iif_cs_sog_en mdd_cs_sog_en iif_dvi_on activity detection composite sync decoder hsync regeneration hsync hsync hs_cs vs_cs hsync hs_regen activity detection 0 1 0 1 mdd_dvi_on hsync hs_dvi 0 1 0 1 0 1 0 1 0 1 activity detection activity detection activity detection activity detection cs_dvi_de sog_en 0 1 0 1 0 1 dvi_de sog 0 1 0 1 vsync csync hsync iff_cs_sog_en 0 1 iif_dvi_on 0 1 0 1 fig.8 synchronization pulse distribution.
2004 apr 05 45 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc217 hsync vsync csync-1 csync-2 csync-3 csync-4 csync-5 fig.9 supported composite sync modes. 7.5.2 h sync regeneration the hsync regeneration reproduces a regular hsync, e.g. in case of equalizing pulses or an absent hsync during vsync. the input selection is shown in table 23. table 23 hsync regeneration input selection 7.5.3 s election of syncs for line - locked pll the source signals of the line-locked pll are selected according to table 24 as either hsync and vsync from the input pins or the composite sync decoder outputs hs_cs and vs_cs. table 24 line-locked pll sync selection 7.5.4 s election of syncs for mode detection and input interface the output selection for input interface and mode detection allows to choose between the input signals hsync and vsync, composite sync decoder outputs hs_cs and vs_cs and the syncs decoded from the dvi input hs_dvi and vs_dvi. the regenerated hsync hs_regen can be selected as source (see tables 25 and 26). table 25 mode detection sync selection; note 1 note 1. x = dont care. hs_regen_in_en hs_regen 0 hs_cs 1 hsync iif_cs_sog_en hs_pll vs_pll 0 hsync vsync 1 hs_cs vs_cs mdd_cs_ sog_en mdd_ dvi_on mdd_hs_ regen_on hs_mdd vs_mdd 0 0 x hsync vsync 0 1 x hs_dvi vs_dvi 1 x 0 hs_cs vs_cs 1 x 1 hs_regen
2004 apr 05 46 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h table 26 input interface sync selection; note 1 note 1. x = dont care. 7.5.5 p in vsync configuration besides serving as input for an external vertical synchronization pulse vsync can be switched as output of the vsync internally derived from (not shown in fig.8): dvi data (vs_dvi) sync-on-green slicer (sog) composite sync decoder (vs_cs). the i/o direction of pin vsync is selected by vsync_out_en of register sync_sel (18h at page 0). in case of output mode, the source is selected by sog_out_en and cs_dvi_de of register sync_sel according to table 27. table 27 pin vsync switching modes; note 1 note 1. x = dont care. 7.6 interrupt generation an interrupt signal is provided at output pin int (active low). the state of int is based on mode detection, auto-adjustment, osd, decoupling fifo and output interface interrupt conditions shown in table 28. table 28 interrupt conditions and description interrupt output pin int is set low (active) whenever one or more of the interrupt flags is high. the interrupt flags are set high, when the corresponding interrupt condition is met: the mode detection interrupt flag is set high when one of the mode measurement bits toggles or a value changes significantly at the vsync or in case of vsync or hsync jitter, depending on which of the conditions are enabled (see section 7.11.1). the auto-adjustment interrupt flag is set high in the moment an auto-adjustment measurement finishes, indicating the result values can be read out. the decoupling fifo interrupt flag is set high whenever the decoupling fifo is full, indicating that the output timing is too slow and a change of the timing is required; otherwise a corrupt output picture will occur. the osd interrupt flag is set high every time a pointer animation frame sequence ends to allow to switch the displayed icon and program the icon for the next turn (see section 7.14.3 ). the output interface interrupt flag is set high when the pixel stream to the output interface is broken, indicating that the output pixel or line rate is too fast. the hsync jitter interrupt flag (int_iif) is set high when line jitter at the analog video input occurs more than a number of times specified in the register ii_hjit, indicating that the other clock edge should be used to sample the hsync and vsync signal. iif_cs_ sog_en iif_dvi_ on iif_hs_ regen_on hs_iif vs_iif 0 0 x hsync vsync 0 1 x hs_dvi vs_dvi 1 x 0 hs_cs vs_cs 1 x 1 hs_regen vsync_ out_en sog_ out_en cs_ dvi_de direction vsync 0 x x input external 1 1 x output sog 1 0 1 vs_dvi 1 0 0 vs_cs interrupt submodule description int_mode mode detection change of input video mode detected int_auto auto-adjustment auto-adjustment ?nished int_?fo decoupling fifo fifo over?ow int_osd osd end of programmed osd frame sequence int_oif output interface fifo under?ow int_iif input interface line jitter occurs (hsync jitter detection)
2004 apr 05 47 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h the interrupt flags are accessible at the global interrupt state register gc_int_stat (feh) and are readable. the flags are only cleared (set to low) if a logic 1 is written into the corresponding bit in gc_int_stat. the interrupt conditions are maskable by the corresponding programming bit in gc_int_mask (fdh); a logic 1 is enabling the particular interrupt condition. 7.7 triple analog-to-digital converter the integrated triple adc samples analog rgb signals of up to 110 mhz with a resolution of 8 bits per colour component and provide automatic brightness and contrast control (see fig.11). the sample clock is generated by the line-locked pll (see section 7.4.3 ), but can also be applied externally. the triple adc is automatically enabled, when analog rgb is selected as input source. the time frames for the adc automatic brightness and gain control are defined by clamp and gain correction pulses generated by the input interface. during these times the adcs adjust brightness and gain according to the programmable brightness and contrast values defined by adc_red_brightness to adc_blue_contrast at registers adc_r_bri to adc_b_con (01h to 06h at page 1), that have to be provided in 2s-complement form between - 128 (80h) and +127 (7fh). not all combinations of contrast and brightness settings are allowed. combining very low contrast (low gain) together with low brightness (more black than black) is not allowed. these combinations would result in a very low input dc level, which would result in the clamp circuit going out of saturation. this would lead to unpredictable behaviour of the clamp level. the allowed region for the gain value is limited between 27 and 110. the clamp and gain correction pulse generation is programmed via registers ii_adc_ctrl and ii_clamp_on to ii_gainc_off (02h to 06h at page 4). clamp pulse generation is enabled by clamp_en. the beginning of the clamp pulse clamp is marked by clamp_on_delay as an offset to the second edge of the hsync pulse, the end by clamp_off_delay as shown in fig.10. the polarity of clamp is given with clamp_pol; logic 1 is high active and logic 0 is low active. during the clamp pulse, that should fall into the hsync backporch, the adcs each match the sampled black level output value to the value given by adc_red_brightness, adc_green_brightness and adc_blue_brightness respectively. the gain correction pulse gainc is the delayed hsync. the first edge of the hsync is delayed by gainc_on_delay and the second edge by gainc_off_delay (see fig.10). the polarity is programmed by gainc_pol; logic 1 is high active and logic 0 is low active. the gain correction pulse generation is enabled by setting gainc_en. during gain correction the adc inputs are connected to a reference voltage and by gain adjustment the output is matched to adc_red_contrast, adc_green_contrast and adc_blue_contrast. handbook, full pagewidth mhc218 vhs rgb data gainc clamp gainc_off_delay gainc_on_delay clamp_on_delay clamp_off_delay fig.10 gain adjustment and clamp pulse generation.
2004 apr 05 48 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth agc bias and reference sync-on-green timing clamp pulse adc clock gain pulse sync output sog enable brightness setting (8-bit) green channel output (8-bit) contrast setting (8-bit) analog part digital part clamp r bias c sog c1 c1 r1 green r1 0.75 r1 adc agc brightness setting (8-bit) red channel output (8-bit) contrast setting (8-bit) clamp c1 c1 r1 red r1 0.75 r1 adc mhc219 agc brightness setting (8-bit) blue channel output (8-bit) contrast setting (8-bit) clamp c1 c1 r1 blue r1 0.75 r1 adc fig.11 analog video input block diagram.
2004 apr 05 49 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.8 dvi interface the digital visual interface (dvi) provides a high-speed digital connection for visual data types that is display technology independent. the interface is primarily focused at providing a connection between a computer and its display device. the dvi uses a communications protocol called transition minimized differential signalling (tmds ? ) (1) . this protocol uses a digital encoding and decoding algorithm to minimize the number of transitions (from high-to-low or vice-versa) within a packet of bits, thereby lowering the energy in the electromagnetic spectrum that the system radiates. using tmds ? , it is generally easier to meet electromagnetic compatibility (emc) requirements. the tmds ? receiver inputs are three data streams of 10-bit frames (tmds ? data) and one clock channel. per channel it recovers and decodes these frames into either 8-bit words or two control bits. it also decodes a data enable (de) signal that indicates when the receiver is receiving active data and when it is receiving control data. the clock indicates the frequency of one tmds ? data packet, i.e. the clock frequency is one tenth of the bit rate. the dvi interface is automatically enabled when selected as input source for the input interface. 7.8.1 hdcp the dvi interface becomes high-bandwidth digital content protection (hdcp) version 1.0 compliant. authentication in hardware is supported. therefore, the saa6713h offers two signals: hscl and hsda. they are the clock and the data signal for the device data channel (ddc) i 2 c-bus that is used in the authentication process.the hdcp keys are stored in an on-chip sram. the system microcontroller is supposed to transfer them from its rom during initialization phase. no external eeprom for key storage is required. the hdcp registers are mapped in table 29. the hdcp related internal configuration registers are placed on page 1 and the bits are mapped in table 30. moreover, a dedicated software reset for the hdcp circuit together with the dvi receiver is introduced. (1) transition minimized differential signalling (tmds) is a subset of panellink technology which is a registered trademark of silicon image, inc. table 29 hdcp registers on the display data channel (ddc) i 2 c-bus; notes 1 and 2 register address r/w reset fields ddc_hdcp_bksv0 00h r x hdcp_bksv[7:0], receiver key selection vector ddc_hdcp_bksv1 01h r x hdcp_bksv[15:8] ddc_hdcp_bksv2 02h r x hdcp_bksv[23:16] ddc_hdcp_bksv3 03h r x hdcp_bksv[31:24] ddc_hdcp_bksv4 04h r x hdcp_bksv[39:32] reserved 05h to 07h - 00h ddc_hdcp_ri0 08h r x hdcp_ri[7:0], link veri?cation response ddc_hdcp_ri1 09h r x hdcp_ri[15:8] reserved 0ah to 0fh - 00h ddc_hdcp_aksv0 10h w x hdcp_aksv[7:0], transmitter key selection vector ddc_hdcp_aksv1 11h w x hdcp_aksv[15:8] ddc_hdcp_aksv2 12h w x hdcp_aksv[23:16] ddc_hdcp_aksv3 13h w x hdcp_aksv[31:24] ddc_hdcp_aksv4 14h w x hdcp_aksv[39:32] reserved 15h to 17h - 00h
2004 apr 05 50 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h notes 1. x = dont care. 2. multibyte values are stored in little endian format on ddc. table 30 hdcp registers con?guration; note 1 note 1. x = dont care. ddc_hdcp_an0 18h w x hdcp_an[7:0], session random number ddc_hdcp_an1 19h w x hdcp_an[15:8] ddc_hdcp_an2 1ah w x hdcp_an[23:16] ddc_hdcp_an3 1bh w x hdcp_an[31:24] ddc_hdcp_an4 1ch w x hdcp_an[39:32] ddc_hdcp_an5 1dh w x hdcp_an[47:40] ddc_hdcp_an6 1eh w x hdcp_an[55:48] ddc_hdcp_an7 1fh w x hdcp_an[63:56] reserved 20h to 3fh - 00h ddc_hdcp_bcaps 40h r 10h [4] hdcp_fast_i2c, 400 khz i 2 c-bus reserved 41h to feh - 00h ddc_hdcp_dbg ffh r/w 00h hdcp_dbg[7:0], debug register bit reset description hdcp_enable 00h 0: hdcp disabled 1: hdcp enabled key_decrypt_enable 00h 0: key is loaded into table without decryption 1: key is decrypted while loading into table hdcp_ddc_addr 74h i 2 c-bus slave address on display data channel key_decrypt_seed x key decryption seed hdcp_bksv x receiver key selection vector hdcp_key_index 00h valid range is 00h to 27h hdcp_key x hdcp_key[55:8]: secret key hdcp_key[7:0]: secret key, writing this register will auto-increment hdcp_key_index register address r/w reset fields
2004 apr 05 51 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.9 input interface the input interface selects video data either provided by the adcs, the tmds ? receiver or externally applied and extracts the input picture for processing. the sample window position and size is programmable, using vertical and horizontal synchronization signals or the dvi data enable signals as reference. alternatively, the picture generator can generate different test pictures with programmable size and horizontal and vertical blanking length. all input interface programming registers are mapped to the i 2 c-bus configuration register page 4. 7.9.1 i nput selection the input source is selected by ext_select and dvi_select (register ii_ctrl, address 00h) as shown in table 31. in case of parallel rgb input, the r component has to be provided at ports pa7 (msb) to pa0 (lsb) in 8-bit format (range 0 to 255), g and b component similarly at ports pb7 to pb0 and ports pc7 to pc0, respectively. the input source can only be changed in a functional reset (see section 7.3). the clock signal edge used to sample the data inputs is specified by ext_clk_edge. if ext_clk_edge is set to logic 1 data is sampled on the rising front-end clock edge; otherwise on the falling front-end clock edge. if convert_2s is set to logic 1 the incoming data is expected to be in 2s-complement form from - 128 (80h) to +127 (7fh); otherwise input data is treated as unsigned values from 0 to 255. data from the internal adcs is always in 2s-complement form. to enable the input interface in_form_on has to be set to logic 1; otherwise no data will be provided for processing. if the picture generator is active, the input formatter will always provide generated data. table 31 input source selection; note 1 note 1. x = dont care. 7.9.2 s ynchronization signals the synchronization pulses are used to identify the frame outline. the sync signals for the input interface are provided by the sync distribution. the complete description of sync switching options is given in section 7.5. if analog or parallel rgb input mode is used, the vertical synchronization pulse (vsync) is connected to pin vsync and the horizontal synchronization pulse (hsync) to pin hsync. a composite synchronization signal is connected to pin hsync. pin vsync can then serve as an output for the generated vertical synchronization pulse. if tmds ? data is selected, the synchronization pulses as well as a de signal are taken from the dvi data stream. for dvi input, dvi_use_hsync defines whether the hsync (dvi_use_hsync = 1) or de signal (dvi_use_hsync = 0) is used for reference purposes. the polarities of hsync, vsync and the de signal are defined by vs_pol, hs_pol and dvi_de_pol. in case of active high polarity, the corresponding bit has to be set to logic 1; otherwise to logic 0. if sync_clk_edge is set to logic 1 all synchronization signals are sampled with the rising front-end clock signal edge; otherwise with falling edge. if delay_vs is set to logic 1, the vsync is delayed in relation to the hsync to prevent line jitter if both occur at the same time, which is monitored by the mode detection. 7.9.3 d efinition of sample window the sample window is defined by in_v_offset, in_h_offset, in_v_length and in_h_length. the vertical offsets are measured from the trailing edge of the vsync pulse. the horizontal offsets are measured from either the first edge of the hsync pulse if hsync_edge is set to logic 1, or the second edge if hsync_edge is set to logic 0. figure 12 shows the horizontal offset for the case hsync_edge is set to logic 0. if a de signal is applied instead of a hsync signal, the leading edge should be used (hsync_edge = 1). if both offsets are set to value 0h, sampling will start with the first pixel in the first line (see fig.13). the length defines width and height of the sampled frame. the vertical sample offset and length are given in lines and the horizontal offset and length are measured in pixels. ext_select dvi_select input source 1 x parallel rgb 0 1 dvi encoded rgb 0 0 analog rgb
2004 apr 05 52 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhb253 vhs rgb data h_offset h_length 0 1 2 3 4 5 n fig.12 rgb data sampling (hsync_edge = 0). handbook, full pagewidth mhc220 vclk pa, pb, pc hsync x 6 5 4 3 2 1 0 x in_h_offset in_h_length fig.13 rgb input port timing using a data enable signal (connected to hsync). 7.9.4 i nterlaced input sampling of interlaced rgb data is enabled by interlace_on. the polarity of the input fields is determined by the number of hsyncs within a frame. the even fields are expected to contain an additional line if reverse_field_id is set to logic 0, or to contain one line less if reverse_field_id is set to logic 1. in the interlaced input mode, the vertical sampling length parameter in_v_length has to be programmed with the length of the actual field (is half the frame length). for de-interlacing, the upscaler has to be programmed accordingly. 7.9.5 p icture generator the input interface contains a picture generator, that can be used to apply simple test pictures instead of using the adc or dvi input. a front-end clock has to be provided (see section 7.4.1). the picture generator is active when test_pic_on is logic 1. it generates a picture of the size defined by in_h_length and in_v_length with additional blanking. the total line length and number of lines are defined by h_length_total and v_length_total. the input interface sample offset is without effect when using the picture generator.
2004 apr 05 53 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h the picture generator consists of a border generation, a vertical and a horizontal ramp and ripple generator, that work independently. the two ramp and ripple generators can be activated separately for each rgb colour component. if h_ramp_r, h_ramp_g, h_ramp_b, v_ramp_r, v_ramp_g or v_ramp_b are set to logic 1, the corresponding ramp and ripple pattern is applied to the corresponding colour component; otherwise the pattern does not contribute to the colour component. if white_border is logic 1, then the border generator is activated for all colours. the border, horizontal and vertical ramp and ripple generator outputs are added up for each colour component. additionally, all colour components are bit reversed if invert is set to logic 1. both ramp and ripple pattern generators work in the same way, only the horizontal generator is based on the column position and the vertical generator on the line number. the ramp and ripple generation is shown in fig.14 for the example of the horizontal generator. the first step size (h_step1 or v_step1) defines the interval after which the increment value (h_colour_inc or v_colour_inc) is added to the current colour. if the second step size (h_step2 or v_step2) is set to 0, the increment is repeatedly added after the first step size interval. if the second step size is not 0, after the increment value was added the second step size defines the position where the decrement value is subtracted from the current colour. after this the first step size and the increment is applied again and so on. range over or underflows are not suppressed and cause the colour values to wrap around. 7.9.6 h sync jitter detection for certain sampling phases the hsync is sampled at its edge and thus unstable. this jitter is detected and another sampling clock edge can be used to avoid it. to detect hsync sample jitter the interval between hsyncs in sample clock cycles is monitored. if the length varies, hsync jitter is detected. as the sample jitter can only change the line length by a maximum of two cycles, only the lowest two bits of the line length have to be considered. if the current line length differs from the previous line, line jitter occurred. the differences of line lengths within a frame are accumulated and the hsync jitter interrupt may be generated when a certain level (hs_jitter_th) is exceeded. during normal operation the jitter detection is only active during the sampled area of the input frame, because the clock rate of the pll generated sample clock might slightly vary during vsyncs. the detection circuit is active at all times during reset or when the input interface is disabled. for the interrupt a state and an enable register exists, as well as a clear flag. the interrupt is level-based, so every frame after a certain number of occurrences until the next vsync the interrupt state is set to logic 1. the jitter detection does not work correctly without a vsync signal. handbook, full pagewidth mhc221 colour value column position 0 255 h_step1 h_step2 h_colour_dec h_colour_inc wrap around fig.14 picture generator ramp and ripple pattern (horizontal generator).
2004 apr 05 54 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.10 colour processing the colour processing performs brightness and contrast adjustment. a programmable offset and gain factor is applied to each rgb colour component. additional gain and offset values can be applied to the pixel data, not affecting r, g and b components separately, but all components at the same time. luminance and chrominance of the pixel data can be directly adjusted, which allows true brightness, contrast and colour saturation using single parameters. register cp_gain_y controls the contrast and cp_offs_y controls the brightness level; both without affecting the colour temperature. registers cp_gain_cb, cp_offs_cb, cp_gain_cr and cp_offs_cr specify gain and offset values for the red and blue saturation of the rgb data. the colour saturation can be shifted simply by using both gain values. the gain and offset values are specified by the 8-bit configuration registers cp_gain_y to cp_offs_b (address 00h to 0bh at page 5). the offset values offset_y, offset_cb and offset_cr for y-c b -c r and offset_r, offset_g and offset_b for rgb colour space are given in the range from - 128 (80h) to +127 (7fh) in 2s-complement form. the gain factors gain_y, gain_cb and gain_cr as well as gain_r, gain_g and gain_b are given in unsigned form, 128 (80h) representing a factor of 1.0. 7.11 rgb mode detection and auto-adjustment the saa6713h can be used to build up auto-scan systems using an external microcontroller. therefore, information about the input resolution and timing are measured by the saa6713h that can be read out via the i 2 c-bus. provided information can be divided into mode detection information to determine the actual rgb input mode and various auto-adjustment features to support the adjustment of the setting of the saa6713h to the new mode. 7.11.1 m ode detection the mode detection determines mode characteristics of the selected video input. the information is provided at the readable i 2 c-bus registers and changes in the values can trigger the interrupt. all the mode detection i 2 c-bus registers are mapped to register page 2. the mode detection uses the back-end clock and cannot run without a present back-end clock. the mode detection is enabled by setting md_on to logic 1. the source of the synchronization pulse signals used by the mode detection is selected by the sync distribution as described in section 7.5.4 (hs_mdd and vs_mdd). the absence of synchronization pulses is indicated by the flags no_vsync and no_hsync. if the corresponding synchronization signal cannot be detected, the flags are set to logic 1; otherwise to logic 0. it should be noted that the hsync is considered undetected, whenever there are more than 65536 back-end clock cycles between two hsyncs. the bits vsync_pol and hsync_pol provide the polarities of the synchronization signals applied. if the synchronization signal is active high, the corresponding flag is set to logic 1; otherwise the flag is set to logic 0. the flag jitter_detected is set to logic 1, when the active edge of hsync and vsync coincide indicating a possible jitter of the syncs, which would lead to an incorrect or unstable result for the number of hsyncs between vsyncs; otherwise the flag is set to logic 0. if a possible jitter between hsync and vsync is detected, a delayed vsync can be used for the measurements instead, which is selected by setting delay_vsync to logic 1; otherwise the original vsync is used. the value of v_lines reports the number of lines within a frame up to a maximum of 2048 lines and v_clocks gives the length of the input frame in back-end clock cycles with a maximum of 2 24 clock cycles. the horizontal period in back-end clock cycles is given by h_clocks, which can be determined in different measurement modes. if h_clocks_accu and h_clocks_cont are both set to logic 0, the h_clocks value is determined once per frame in the middle of the frame. if h_clocks_accu is logic 1, then h_clocks gives the accumulated length of 16 lines also measured in the middle of the frame. if h_clocks_accu is logic 0, but h_clocks_cont is set to logic 1, then the h_clocks measurement is performed every line of the frame, including the vertical blanking and vsync time. the maximum horizontal period is 65536 back-end clock cycles. the measurement results can be used to generate a mode detection interrupt. each flag or value can be individually enabled for interrupt generation by setting the corresponding interrupt enable bit jitter_int_en, v_lines_int_en, h_clocks_int_en, v_clocks_int_en, no_vsync_int_en, no_hsync_int_en, vsync_pol_int_en or hsync_pol_int_en to logic 1. changes of v_lines, v_clocks and h_clocks only cause an interrupt if the difference between new and old value is greater than four.
2004 apr 05 55 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h additionally, the mode detection interrupt can be generated on the falling edge of every vsync, which is enabled if vsync_int_en is set to logic 1. the states of each interrupt condition vsync_int, jitter_int, vsync_pol_int, hsync_pol_int, no_vsync_int, no_hsync_int, v_lines_int, h_clocks_int and v_clocks_int can be read out at registers md_int_hi and md_int_lo (0ah and 0bh). whenever an interrupt condition is met, the particular flag is set to logic 1. if clear_int at md_ctrl (00h) is programmed with logic 1, all interrupt flags are cleared. if int_lock is set to logic 1, all flags and values are frozen in the moment an interrupt occurs until clear_int is set to logic 1 the next time. to disable the dvi delock interrupt by software when no dvi clock is present, the dvi_delock_int_mdd_en bit in the register gc_misc1 (fbh) has to be programmed. this has to be considered in particular if no dvi clock is present during power-on reset. 7.11.2 s ync activity detection activity detection for both dvi and avi horizontal and vertical sync is provided and is independent from whether dvi or avi is selected as input in the input interface. moreover, the vertical sync output of the csync slicer and the sync-on-green signal from the sync separator are checked permanently for activity. an interrupt may be generated on any change of activity. interrupts can be masked with a set of interrupt enable bits. writing a logic 1 to the existing clear_int bit will clear this interrupts. for activity bits, logic 0 means inactive and logic 1 means active. for sync interrupt bits, logic 0 means disabled and logic 1 means enabled. for sync active interrupt bits, logic 0 means no interrupt and logic 1 means interrupt pending. the sync-on-green activity detection is only an indicator that the digital output of the sync slicer is active. the line-locked pll with its lock flag should be used to distinguish a real sync-on-green from disturbances resulting from the image data on the green channel. table 32 line pll lock 7.11.3 a uto - adjustment there are four auto-adjustment modes: active area detection brightest and lowest pixel search pixel measurement phase distortion measurement. the programming registers for all four modes are shared. bit aa_mode selects the auto-adjustment mode according to table 33. table 33 auto-adjustment modes in each mode, reference colours or reference coordinates have to be programmed (into bits ref_colour_0, ref_colour_1 or ref_row_0, ref_col_0, ref_row_1, ref_col_1 respectively). the auto-adjustment is activated by writing to the aa_ctrl register and started synchronized to the beginning of the next frame. the function is then applied for a number of frames defined in aa_cycles. after performing the auto-adjustment for this number of frames, an interrupt can be generated. the different aa-functions have two further aa_submode bits to control the functionality of each auto-adjustment mode. 7.11.3.1 active area detection with the active area detection feature it is possible to measure the number of blanking pixels and lines between the synchronization pulses and the active video. to distinguish between blanking and active video the threshold colour values ref_colour_0 and ref_colour_1 have to be defined. parameter ref_colour_0 is used to determine the start of the active video area. if the sample value of at least one of the three colour components is above this value the pixel is treated as upper left corner of active video. llpll_inlock function 0 line pll out-of-lock 1 line pll in lock aa_mode[1:0] function 00 active area detection 01 brightest and lowest pixel search 10 pixel measurement 11 phase distortion measurement
2004 apr 05 56 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h its coordinates are stored in eval_col_0 (x-coordinate) and eval_row_0 (y-coordinate). all pixels are also compared with the ref_colour_1 values. if one of the current colour values is bigger, the coordinates are saved in eval_row_1 and eval_col_1. at the end this value defines the lower, right corner of the active area. the values are kept in eval_row_0/1 and eval_col_0/1 until another mode or another area detection without resample is started. it is also possible to start measuring with the preceded values in the resample submodes. in submodes without resample, the results will not be smaller than the preceding values. there are two different modes available: in the enhanced mode all input data is used for measurement (see fig.15) in the non-enhanced mode only one input line, defined by ref_row_1 and one input column, defined by ref_col_1, is used (see fig.16). the needed sample offsets for the input interface can be directly obtained by reading out the eval_row_0 and eval_col_0 values. the number of active pixels per line and lines per field is generated by subtracting the eval_row_0, eval_col_0 value from the eval_row_1, eval_col_1 value. dependent on the sampling settings of the input interface, the eval_row_0 and eval_col_0 values usually correspond to the horizontal and vertical backporch of the incoming video signal and the active video, of course, meets the active area of that stream. the calculated active pixels per line value can be used for adjusting the line-locked pll which is generating the adc sample clock in a way that this value matches the number of expected active pixels per line in the actual graphics mode. there are four submodes available, as shown in table 34. in the non-enhanced modes, the active area detection is not performed over the whole frame as in the enhanced modes, but only within the line and within the column programmed by ref_row_0 and ref_col_0. for correct results, these reference values have to be previously set inside the active area of the picture. if a submode with initial values is selected eval_col_0/1 and eval_row_0/1 are reset to their initial values before evaluation. the brightest and lowest pixel value inside the active area is available in ref_pixel_red_0/1, ref_pixel_green_0/1 and ref_pixel_blue_0/1. the evaluated values for the lowest colour value pixel cannot be lower than the lowest threshold value. the dvi data enable signal can be used for the active area measurement of the auto-adjustment. if dvi_de_auto_adj of input interface register ii_sync_ctrl (01h at page 4) is set to logic 1, the active area position and size is directly derived from the data enable signal; if dvi_de_auto_adj is logic 0, then the picture contents are used for the measurement. mhc222 handbook, halfpage start > ref_colour_0 ref_colour_0 ref_colour_1 eval_row_1 eval_row_0 eval_col_0 eval_col_1 > ref_colour_1 fig.15 enhanced mode. active area: shaded. handbook, halfpage mhc223 start > ref_colour_0 ref_colour_0 ref_colour_1 eval_row_1 ref_row_1 eval_row_0 eval_col_0 eval_col_1 > ref_colour_1 ref_col_1 fig.16 non-enhanced mode. active area: shaded.
2004 apr 05 57 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h table 34 mode 00 (active area detection) bit description input values aa_submode[1:0] submode 00: enhanced mode with resampling, no initial values, evaluation over full frame 01: non-enhanced mode with resampling, no initial values, evaluation in one row and column 10: enhanced mode with initial values 11: non-enhanced mode with initial values aa_cycles[1:0] measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: until next change in position value ref_col_0[10:0] reference column (for non-enhanced mode) ref_row_0[11:0] reference row (for non-enhanced mode) ref_colour_0[23:0] threshold value of backporch colour (upper left) ref_colour_1[23:0] threshold value of frontporch colour (lower right) output values eval_col_0[15:0] active area upper left corner column; will be set to ffff before evaluation in mode without resample eval_row_0[15:0] active area upper left corner row; will be set to ffff before evaluation in mode without resample eval_col_1[15:0] active area lower right corner column; will be set to 0000 before evaluation in mode without resample eval_row_1[15:0] active area lower right corner row; will be set to 0000 before evaluation in mode without resample ref_pixel_red_0[7:0] maximum red component colour value over the whole frame ref_pixel_green_0[7:0] maximum green component colour value over the whole frame ref_pixel_blue_0[7:0] maximum blue component colour value over the whole frame ref_pixel_red_1[7:0] minimum red component colour value within active area ref_pixel_green_1[7:0] minimum green component colour value within active area ref_pixel_blue_1[7:0] minimum blue component colour value within active area
2004 apr 05 58 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.11.3.2 brightest and lowest pixel search the brightest and lowest pixel search determines the position of the brightest pixels and the lowest pixels in a predefined area. therefore, the area is scanned from the upper left to the lower right corner. the pixel value and the position values are readable. four submodes are available to search independently for rgb minimum and maximum values (see table 35). table 35 mode 01 (minimum and maximum search) bit description input values aa_submode[1:0] submode 00: maximum of red and green 01: maximum of blue 10: minimum of red and green 11: minimum of blue aa_cycles[1:0] measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: 16 frames ref_col_0[10:0] search area upper left corner column ref_row_0[11:0] search area upper left corner row ref_col_1[10:0] search area lower right corner column ref_row_1[11:0] search area lower right corner row output values eval_col_0[15:0] pixel position 0 column (according to submode) eval_row_0[15:0] pixel position 0 row (according to submode) eval_col_1[15:0] pixel position 1 column (according to submode) eval_row_1[15:0] pixel position 1 row (according to submode) ref_pixel_red_0[7:0] red channel colour value at evaluated position 0 ref_pixel_green_0[7:0] green channel colour value at evaluated position 0 ref_pixel_blue_0[7:0] blue channel colour value at evaluated position 0 ref_pixel_red_1[7:0] red channel colour value at evaluated position 1 ref_pixel_green_1[7:0] green channel colour value at evaluated position 1 ref_pixel_blue_1[7:0] blue channel colour value at evaluated position 1
2004 apr 05 59 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.11.3.3 pixel measurement for exact measurements within the incoming video stream, two reference pixel positions can be defined with ref_row_0, ref_col_0 and ref_row_1, ref_col_1. the r, g and b components of this pixel are sampled and available at ref_pixel_red_0/1, ref_pixel_green_0/1 and ref_pixel_blue_0/1. the reference pixel colour values can be used for fine tuning the external pll in frequency and phase and for colour gain adjustment. three submodes are available to output the maximum value, the minimum value or the mean value at the dedicated position (see table 36). to simplify the measurements, the values can be taken as a single snapshot representing the momentary value of the pixel at the reference position or they can be build up over several frames, which is activated by programming the number of frames to bits aa_cycles. table 36 mode 10 (pixel measurement) bit description input values aa_submode[1:0] submode 00: maximum of pixel at dedicated positions 01: minimum of pixel at dedicated positions 10: mean value of pixel at dedicated positions 11: mean value of pixel at dedicated positions aa_cycles[1:0] measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: 16 frames ref_col_0[10:0] pixel position 0 column ref_row_0[11:0] pixel position 0 row ref_col_1[10:0] pixel position 1 column ref_row_1[11:0] pixel position 1 row output values ref_pixel_red_0[7:0] red channel colour value at position 0 ref_pixel_green_0[7:0] green channel colour value at position 0 ref_pixel_blue_0[7:0] blue channel colour value at position 0 ref_pixel_red_1[7:0] red channel colour value at position 1 ref_pixel_green_1[7:0] green channel colour value at position 1 ref_pixel_blue_1[7:0] blue channel colour value at position 1
2004 apr 05 60 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.11.3.4 phase distortion measurement to help adjusting the phase for the adcs, the saa6713h has a built-in phase distortion measurement which is calculating a 30-bit indicator value of a defined area of the video signal (see table 37). the area for phase distortion measurements may contain active video or blanking. the area is defined by applying the upper left and lower right corner of the area to ref_col_0, ref_row_0 and ref_col_1, ref_row_1 respectively. assuming a stable input picture with different pixel values inside the measurement window, the phase adjustment can be done by shifting the adc phases and reading out the phase distortion indicator value of bits eval_row_0 and eval_col_0 for the maximum distortion value and eval_row_1 and eval_col_1 for the minimum distortion value. the best sampling phase corresponds to the highest value of the phase distortion indicator. this phase distortion value could also be used for the frequency adjustment by sweeping the input frequency around the assumed target frequency. when auto-adjustment is in phase distortion mode, a signature is calculated for each frame. changes inside the input stream can be detected by reading the signature bits ref_pixel_blue_0, ref_pixel_red_1, ref_pixel_green_1 and ref_pixel_blue_1. for still pictures, the signature does not change. table 37 mode 11 (phase distortion measurement) bit description input values aa_submode[1:0] not used aa_cycles[1:0] measurement interval 00: 1 frame 01: 4 frames 10: 8 frames 11: 16 frames ref_col_0[10:0] measurement area upper left corner column ref_row_0[11:0] measurement area upper left corner row ref_col_1[10:0] measurement area lower right corner column ref_row_1[11:0] measurement area lower right corner row output values eval_col_0[15:0] maximum of distortion[15:0] eval_row_0[15:0] maximum of distortion[29:16] eval_col_1[15:0] minimum of distortion[15:0] eval_row_1[15:0] minimum of distortion[29:16] ref_pixel_blue_0[5:0] signature[29:24] ref_pixel_red_1[7:0] signature[23:16] ref_pixel_green_1[7:0] signature[15:8] ref_pixel_blue_1[7:0] signature[7:0]
2004 apr 05 61 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.11.3.5 how to use auto-adjustment table 38 auto-adjustment steps 7.12 decoupling fifo the decoupling fifo allows an output line generation independent of the input line timing. the fifo holds 1280 pixels, and either buffers incoming data when the vertical upscaling does not require any or holds back a line to be able to provide a continuous data stream in case of vertical downscaling. the fifo output is locked after every line if line_lock is set to logic 1; otherwise after every frame and only released if the fifo level exceeds the threshold level, given by fifo_threshold in units of 8 pixels. 7.13 scaling the saa6713h features separate scaling engines for upscaling and downscaling, for both horizontal and vertical processing. two separate scaling units are implemented to perform upscaling and downscaling. 7.13.1 d ownscaling the downscaling engine is used for reducing the incoming rgb data stream, i.e. for displaying high resolution input frames on panels with a smaller resolution. the scaling ratio can be programmed independently for both horizontal and vertical downscaling units. the algorithm uses pixel accumulation, achieving a minimum scaling factor of 1 64 . if the downscaler is used, it must be enabled by setting dsc_en to logic 1. setting-up the desired downscaling ratios is achieved by programming the scaling increments dsc_v_incr, dsc_v_incr_corr, dsc_h_incr and dsc_h_incr_corr. this must be done for both vertical and horizontal scaling. where xx is equivalent to dsc_v_incr or dsc_h_incr and yy is the fraction of the result in 1 100 . this is the value for programming the increment correction values dsc_v_incr_corr and dsc_h_incr_corr. example: from sxga to xga. horizontal: this means dsc_h_incr = 51 and dsc_h_incr_corr = 20. vertical: this means dsc_v_incr = 48 and dsc_v_incr_corr = 00. 7.13.2 u pscaling the upscaling engine is used for enlarging the incoming video frames. the magnification can be programmed individually for horizontal and vertical scaling. the maximum scaling factor for both directions is 64. the implemented filter algorithm uses interpolation with pixel enhancement, based on a free programmable transition function. therefore, it is possible to define the transition between two calculated pixels to obtain different sharpness characteristics. this transition function must be defined in the 48 8 bits look-up table, with a number ranging from 0 to 64. different functions can be programmed for horizontal and vertical scaling. the upscaler must be activated by usc_en. to set up the zoom factor, the scaling increments v_scale_incr, v_scale_corr, h_scale_incr and h_scale_corr must be programmed. where xx is equivalent to v_scale_incr or h_scale_incr and yy is the fraction of the result in 1 100 . this is the value for programming the increment correction values v_scale_corr and h_scale_corr. example: from xga to sxga. horizontal: this means h_scale_incr = 80 and h_scale_corr = 00. vertical: this means v_scale_incr = 85 and v_scale_corr = 33. remark: the last digit must be rounded up: 85.33 results in 1023.96 lines, but the upscaler will display only 1023 lines. step action 1 program position values according to mode 2 program mode, submode and cycle values to start auto-adjustment 3 wait until interrupt appears 4 read the according values incr number_of_output_pixels number_of_input_pixels ------------------------------------------------------------------ - 64 xx.yy = = 1024 1280 ------------- 64 51.20 = 768 1024 ------------- 64 48.00 = incr number_of_output_pixels number_of_input_pixels ------------------------------------------------------------------ - 64 xx.yy = = 1280 1024 ------------- 64 80.00 = 1024 768 ------------- 64 85.33 =
2004 apr 05 62 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.13.3 h orizontal flipping the saa6713h provides the possibility to flip horizontally the incoming picture. as flipping needs a line memory, both the downscaler and the upscaler have a flip programming register. when using the downscaler flip mode (flip_h = 1), no vertical downscaling can be performed. this is to be used when upscaling and flipping have to be programmed. in case downscaling and flipping shall be performed, flipping has to be done inside the upscaler by setting usc_h_flip to logic 1. 7.14 on screen display the on screen display consists of three different and independent parts: osd text, osd bitmap and osd pointer, where the osd text is used as the main osd part to build an application specific on screen menu (osm). the bitmap part of the osd is intended to be used for company logo or can be used as the backdrop of an osm with up to 16 individual colours. as an addition for the graphical user interface in the osm, the osd pointer part allows a hardware cursor that is overlaid over picture data and the other osd data. its intention is to be used as a mouse pointer for selecting and modifying osm items. each of the three osds can be zoomed independently with pixel repetition by the factors 1, 2, 3 and 4 and can be rotated by 90 degrees clockwise, horizontally and vertically mirrored, if desired. all colour information used by the three osd parts are organized in global colour tables (palettes) which define a certain colour each with 24-bit rgb data. these colour and palette registers are located at register page 9 (osd colours). 7.14.1 osd text the osd text is a character based approach and consists of a window definition ram, a font definition ram and a font definition rom. the window definition ram gives the information about the data that is going to be displayed. it is organized as a character-based matrix that is free definable in terms of width and height (registers osdt_wx and osdt_wy) as long as the resulting number of elements does not exceed the maximum number of 1024 elements. each element of this window matrix can directly accessed using the cursor registers osdt_curx and osdt_cury. the display position where the osd text window is displayed in the picture, can be freely defined via the registers osdt_px and osdt_py. in fig.17 an example of an 11 5 character window is shown that uses a total number of 55 elements. it should be noted that the parameters osdt_wx and osdt_wy are given in character units, whether the offset of the window is given in pixel units. the real size of the osd text window depends on the actual defined font resolution (osdt_fr_x and osdt_fr_y), the actual zoom factor (zoom[1:0] value of 1, 2, 3 or 4 in register osdt_ctrl0) and the rotate flag (rotate_right in register osdt_ctrl0). so, the overall size of the osd text in pixel is derived by calculating osdt_wx zoom osdt_fr_x respectively osdt_wy zoom osdt_fr_y. in addition to this nominal window size, the optional window shadow feature (bit window_shadow) will extend the active osd text area by the defined width and height (osdt_wshad) multiplied with the actual zoom factor. keep in mind that during rotation of the osd, the core osd text height and width will be visible exchanged, but the anchor position and the window shadow will not be seen (see fig.18). from the application (software) point of view, the osd programming does not change no matter if horizontal, vertical or flip flags are used or not. only the display position registers (anchor) osdt_px and osdt_py must be chosen in a way that the now transposed osd text window fits still in the picture. all matrix and font based accesses are automatically transposed, not even the index of the elements (cursor) has to be considered.
2004 apr 05 63 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc224 osdt_wx (= 11) osdt_px osdt_py ... ... 52 53 54 8910 567 234 01 15 16 12 13 14 11 osdt_wy (= 5) picture 0,0 osdt_fr_x zoom osdt_fr_y zoom osdt_curx = 5 osdt_cury = 3 fig.17 osd window definition. handbook, full pagewidth mhc225 osdt_curx = 5 osdt_cury = 3 picture 02 1 345678910 11 12 13 14 15 16 ... ... 52 53 54 osdt_px osdt_py osdt_fr_x zoom osdt_fr_y zoom osdt_wy (= 5) osdt_wx (= 11) fig.18 osd window horizontal, vertical, flip, rotate.
2004 apr 05 64 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h to allow easy access to the window definition when writing data to the osd text, the cursor will perform an auto-increment function to the next right element (or to a new line, if the line ends) each time an element is written to the ram which is allowing an i 2 c-bus burst transmission to define the window contents. the actual cursor values can be read back at any time. each element of the osd text window consist of 23 bits. they represent the property of an osd text character. the elements are accessible via the osdt_prop2, osdt_prop1 and osdt_prop0 registers (see table 39). all information encoded with these osdt_prop registers is valid for one character only, so the look of an osd text can be changed mainly on a character base. the colour definition elements bg_colour[2:0] and fg_colour[2:0]/palette[2:0] are not defining a colour directly but are assigning a value from the global osd colour tables which are defined within register page 9. for single colour characters, the user can select one of the eight possible foreground colours and one of eight possible background colours. for multicolour characters one out of eight possible colour palettes is chosen; each defining four colours (1 background and 3 foreground) to be used within this character. the information whether a character is a multicolour character or a single colour character is derived from the charcode and the value of sc_startcode (osdt_sc_hi and osdt_sc_lo) that defines the multi or single character mapping inside the font ram. table 39 osd property registers table 40 osd property registers bit description register d7 d6 d5 d4 d3 d2 d1 d0 osdt_prop2 blink[1:0] shadow bg_trans fg_trans bg_alpha fg_alpha osdt_prop1 bg_colour[2:0] fg_colour[2:0]/palette[2:0] rom charcode[8] osdt_prop0 charcode[7:0] bit description blink[1:0] de?nes the blink mode of the character 00: blinking is off 01: blinking of foreground only 10: character is inverse, no blinking 11: blinking by inversion of foreground and background colour shadow if set to logic 1, the character will be displayed with an 1 pixel horizontal and vertical shadow bg_trans if set to logic 1, the background colour is displayed transparent fg_trans if set to logic 1, the foreground colour is displayed transparent bg_alpha if set to logic 1, the background will not be displayed solid but alpha-blended with picture data using the global de?nable background alpha-blending factor (osdt_bga) fg_alpha if set to logic 1, the foreground will not be displayed solid but alpha-blended with picture data using the global de?nable foreground alpha-blending factor (osdt_fga) bg_colour[2:0] de?nes which of the 8 de?nable text background colours is used for this character fg_colour[2:0]/ palette[2:0] shared programming bits; fg_colour de?nes which of the 8 text foreground colours is used for this character (only valid if charcode points to a single colour character) and palette de?nes used multicolour palette (only valid if charcode points to a multicolour character) rom if set to logic 1, the character is selected from rom; if set to logic 0, then the character is selected from ram charcode[8:0] indicates the desired character inside the font rom/gen or the font ram
2004 apr 05 65 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h different property register write modes can be selected, allowing to accelerate the i 2 c-bus programming of osd windows with characters sharing the contents of one or more property registers. parameter write_mode of register osdt_mask (see table 41) controls which of the three property registers osdt_prop2 to osdt_prop0 have to be updated until the character information is internally written into the window ram. the registers are activated by write_mode according to table 43. only once all activated registers have been updated via the i 2 c-bus, the character is written into the window ram and the cursor position defined by osdt_curx and osdt_cury is advanced to the next window element. the information of an inactive property register is still included in the character definition, but the register does not have to be rewritten for every new character definition. example 1: for a single-coloured ascii character-based osd, write_mode is set to 001 and property registers osdt_prop2 and osdt_prop1 have only to be defined initially, all window elements are then defined by consecutive writing of osdt_prop0. with every write operation to osdt_prop0 a new window element is defined. the i 2 c-bus burst access is also supported for the property registers specified by parameter write_mode as specified in table 43. the active property register values of consecutive window elements can be transmitted in the i 2 c-bus burst mode without the requirement of repeating device addressing and the transmission of the subaddress for every character or property register. example 2: for a multi-coloured osd, write_mode is set to 6 to activate only osdt_prop1 and osdt_prop0. osdt_prop2 is set initially. the osd can then be programmed with one i 2 c-bus write burst consisting of device addressing byte, the osdt_prop1 subaddress followed by osdt_prop1 value of first character, osdt_prop0 value of first character, osdt_prop1 value of second character, osdt_prop0 value of second character, osdt_prop1 value of third character etc. after each transmission of an osdt_prop0 value the character definition is transferred into the window ram. the masking bits (see table 42) are used as a data filter that specifies which parts of the complete osdt_prop word (23 bits) are written to the ram and which are masked out. each attribute will only be updated in the osd text window ram element if its mask bit is set to logic 1. if that is not the case, the window ram will ignore this part of the osdt_prop register and will keep up its previously defined value for this part at the selected osd text window element. table 41 osdt_mask register table 42 osdt_mask register bit description register d7 d6 d5 d4 d3 d2 d1 d0 osdt_mask blink_mask shadow_mask bg_mask fg_mask code_mask write_mode[2:0] bit description blink_mask 1: blink[1:0] property will be written according to actual osdt_prop2 settings 0: blink[1:0] property will not be modi?ed shadow_mask 1: shadow property will be written according to actual osdt_prop2 settings 0: shadow property will not be modi?ed bg_mask 1: all background information will be written according to actual property settings (osdt_prop2: bg_trans, bg_alpha and osdt_prop1: bg_colour) 0: the background property will not be modi?ed fg_mask 1: all foreground information will be written according to actual property settings (osdt_prop2: fg_trans, fg_alpha and osdt_prop1: fg_colour) 0: the foreground property will not be modi?ed code_mask 1: the charcode property will be written according to actual property settings (osdt_prop1: rom, charcode[8] and osdt_prop0: charcode[7:0]) 0: the charcode property will not be modi?ed write_mode[2:0] write mode selection (see table 43)
2004 apr 05 66 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h table 43 write mode selection write_ mode[2] write_ mode[1] write_ mode[0] active i 2 c-bus registers i 2 c-bus subaddress auto-increment handling 000 -- 0 0 1 osdt_prop0 burst access to osdt_prop0 0 1 0 osdt_prop1 burst access to osdt_prop1 0 1 1 osdt_prop1 and osdt_prop0 sequential access to osdt_prop1 ? osdt_prop0 ? osdt_prop1 ? etc. 1 0 0 osdt_prop2 burst access to osdt_prop2 1 0 1 osdt_prop2 and osdt_prop0 sequential access to osdt_prop2 ? osdt_prop0 ? osdt_prop2 ? etc. 1 1 0 osdt_prop2 and osdt_prop1 sequential access to osdt_prop2 ? osdt_prop1 ? osdt_prop2 ? etc. 1 1 1 osdt_prop2 to osdt_prop0 sequential access to osdt_prop2 ? osdt_prop1 ? osdt_prop0 ? osdt_prop2 ? etc. the combination of the mask bits and the write_mode already provides a powerful way to speed any osm drawings by minimizing the needed i 2 c-bus transmissions, but there is even more hardware support for defining an area inside the osd text window which has the same element property for all elements within its boundaries. an area can be defined using the upper-left and bottom-right cursor coordinates inside the osd text window matrix using the osdt_faulx, osdt_fauly, osdt_fabrx and osdt_fabry registers. the execution of the writing is initiated by writing a logic 1 to areafill_start (register osdt_ctrl0) and as before, the current value of the complete 23-bit osdt_prop word is written to each element of the defined area. of course, the mask bits are still valid and can be used also during an areafill execution. so, this function can not only be used to overwrite and clear areas inside the osm, it can also be used to highlight or blink certain areas in the osm. it should be noted that it might be needed to set the write_mode to 000 if you want to change any of the osdt_prop settings previous to an areafill and assure that no write and cursor auto-increment is done accidentally. as described before: all definitions of the osd window elements are just defining the property of a character and are pointing to a font definition by the charcode attribute. the real character contents are taken from either the font rom/gen part or the font ram part of the osd text indexed by that charcode. the font definition rom/gen is already providing a large amount of predefined fonts as illustrated in fig.19.
2004 apr 05 67 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... n dbook, full pagewidth mhc226 1 0 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 24 36 589 7 abcde f 1 0 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e generated 1f 24 36 589 7 abcdef fig.19 rom/gen character codes.
2004 apr 05 68 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h the character codes from 000h to 15fh (see table 44) are rom defined characters with the natural resolution of 12 18 pixels, so the font resolution defined via osdt_fr_x and osdt_fr_y should be set to 12 and 18 to achieve optimal viewing results. if the actual font resolution is defined greater than 12 18, all rom characters will be centred automatically inside the programmed font size; if it is less than 12 18 the characters will be cropped. this handling allows rom and ram characters to be displayed together in one osd, even if the ram font size does not fit the rom size of 12 18 pixels. looking at fig.19 it is easily seen that the rom is using six different subareas for the charcode. the addresses from 160h to 1f6h are mapped to the internal character generators (gen). despite the real rom definitions these characters do not have a native resolution instead they will always be displayed in the actual defined font resolution (osdt_fr_x and osdt_fr_y) itself. while the border characters of the font gen are kept fixed and just adapted to the used font size, the slider parts are generated based on its parameters osdt_slp1 and osdt_slp0 (see table 45). table 44 rom mapping address (hex) contents 000 to 01f multicolour, dual character symbols 020 to 02f multicolour, single character symbols 030 to 04f single colour, dual character symbols 050 to 05f single colour, single character symbols 060 to 112 single colour, ansi like character set with ascii mapping (ascii code + 60h) 113 to 15f single colour, basic japanese font set 160 to 1d1 single colour, border and line characters 1d1 to 1f6 multicolour generated slider parts table 45 slider property registers table 46 slider property registers bit description register d7 d6 d5 d4 d3 d2 d1 d0 osdt_slp1 slider_border[3:0] slider_offset[3:0] osdt_slp0 slider_style slider_gap[3:0] bit description slider_offset[3:0] distance from the character border to the generated slider in pixel slider_border[3:0] thickness of slider border in pixel slider_gap[3:0] gap between slider border and slider core in pixel slider_style 0: ?ll; middle slider parts are solidly ?lled from left to right and from bottom to top 1: peak; middle slider parts are created with a single marker at reference position
2004 apr 05 69 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc227 s e m fg = 16 m fg = 16 m fg = 7 m fg = 0 colour 0 (bg) colour 1 (fg) colour 2 (fg) colour 3 (fg) offset border gap osdt_fr_x osdt_fr_y fig.20 multicolour slider generation. when putting together a slider with multiple characters (see fig.20), a slider always consists of three basic parts: a start part (s), a middle part (m) with different fill grades (fg) and an ending part (e). the start part is always located at address 1d2h (horizontal) respectively 1f6h (vertical) and the end part is always located at 1e3h respectively 1e4h. the characters in between the start and the end character correspond to different fill grades of the middle part that are needed to give a subcharacter precision in a custom slider. in this system the middle part uses a natural resolution of 16 pixel per character which is resulting in 17 different characters from empty to full. if the display size is different from the natural resolution, either some fill grades will be skipped or some fill grades will be doubled within the 17 characters that are reserved to represent the middle parts. anyhow mathematically, it is always correct to use the slider resolution of 16 to calculate the fill grade of the last partly filled slider part and use this value directly to index to the correct middle part. using this approach results in an overall slider resolution equal to the number of used middle characters multiplied by 16 to graphically display any values within an osm either with a fill bar or a single marker. to achieve more flexibility in the osd look, 4 kbyte of user definable ram can be used in addition to the rom/gen characters. this font definition ram can contain a downloadable mixed multicolour or single colour font which is in terms of character size freely programmable via osdt_fr_x and osdt_fr_y registers but has to be between 8 8 and 32 32 pixels. this font resolution is valid for all characters inside the ram, no matter if they are defined in single colour or multicolour but a single colour pixel can be stored with one while a multicolour pixel occupies two bits inside the font ram. for single colour characters a pixel of value 0 will be displayed as background and a pixel data of value 1 will be displayed as foreground according to the defined colour values in the osdt_prop registers and the osd colour definitions on register page 9. for multicolour characters always two bits are taken for each pixel that directly map to the four colour value inside the selected multicolour palette which is also defined in register page 9 and is selected within osdt_prop. the font ram (see table 47) can store a maximum number of 512 8 8 single colour characters which corresponds to the 9-bit charcode in the osdt_prop registers. using multicolour definitions that need two bits per pixel and/or larger font resolution reduces of course the number of possible characters to be stored in the font ram.
2004 apr 05 70 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h the multicolour font definitions have to start always from address 0 and the start of the single colour definitions is indicated by the configurable single colour start code (osdt_sc register). this means all the characters with charcodes below the osdt_sc value are treated as multicolour and all charcodes above this value are handled as single colour characters. to use only multicolour characters in the ram font set this value must be set to an unreachable value. due to the ram size of 4 kbyte a multicolour 8 8 font with 2 bits per pixel can hold 256 characters as maximum so it is enough to set only bit 8 in osdt_sc_hi register to logic 1. to use only single colour definitions set the complete osdt_sc pointer simply to 000h. a character is stored in the font ram using the osdt_cc_hi, osdt_cc_lo, osdt_cmask and osdt_cdef registers where osdt_cc gives the charcode of the character to be defined and osdt_cdef and osdt_cmask are used for the data bits and the according mask using 8 bits at a time. the data format written to osdt_cdef has to be msb aligned representing the following pixel of the character with the pixel sequence processed from top to bottom and left to right. as mentioned before, a single colour pixel is represented with one bit while a multicolour pixel needs two bits to be described. so each definition of a character will need multiple writes to osdt_cdef (8 bits at a time) until the whole character is completed. the total number of bytes to be transmitted is depending on the defined font size and if the character uses a single or multicolour definition. table 47 examples of possible font ram con?gurations font size storable characters colour maximum number 8 8 single colour only 512 multicolour only 256 mixed example 256 single colour and 128 multicolour 12 16 single colour only 170 multicolour only 85 mixed example 100 single colour and 35 multicolour 12 18 single colour only 151 multicolour only 75 mixed example 121 single colour and 15 multicolour 9 13 single colour only 280 multicolour only 140 mixed example 200 single colour and 40 multicolour 24 24 single colour only 56 multicolour only 28 mixed example 40 single colour and 8 multicolour 32 32 single colour only 32 multicolour only 16 mixed example 24 single colour and 4 multicolour
2004 apr 05 71 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc228 osdt_fr_x (= 9) osdt_fr_y (= 11) byte 1 byte 3 byte 2 byte 4 ... osdt_fr_x (= 9) osdt_fr_y (= 11) byte 1 byte 3 byte 2 byte 4 ... fig.21 data format of the osd font ram. b. multicolour definition sequence (needs 9 11 2 = 198 bits ? 25 bytes). a. single colour definition sequence (needs 9 11 = 99 bits ? 13 bytes). it should be noted that the characters are not stored byte-aligned in the internal ram due to the programmable font sizes (see fig.21). due to this, a bit-exact address is internally needed that points to the first bit of a character inside an 8-bit data word. this internal character base address is calculated new, each time data is written to either the osdt_cc_hi or osdt_cc_lo register and is incremented by 8 bits on each write to osdt_cdef. during each write the actual value of the osdt_cmask register is used. so for an 8 8 single colour character to be defined, simply set osdt_cc to the desired charcode, set all bits of osdt_mask to logic 1 and write 8 times to osdt_cdef to define the complete character. for a 9 9 single colour character (needs 81 bits) you have to do 11 writes to osdt_cdef, even if only the msb of the 11th transmission is used and the remaining 7 bits stay unused. one could now either use masked writing to mask those bits 6 to 0 out (so the following character definition is not touched) or immediately continue with the definition of the next character and simply connect the next character data to bit 6 down to bit 0. because the ic cannot determine which functionality is desired, the user can select this by setting the osdt_cc register. if an automatic masking at the end of each character is desired, the flag single_char_def (osdt_cc_hi[7]) can be set to logic 1. this means that before the next character definition the desired charcode must be written again, because the internal bit address does not longer match with the following character base address. otherwise, if this bit is kept to logic 0, the internal bit address is continued over character boundaries allowing multiple bit-packed character transmission in a sequence. only the last definition might need a manual masked writing in case of an address space overflow or if any needed data is present at higher charcodes. to reduce the programming time for the font ram, an auto-increment function is used internally so that an i 2 c-bus burst transmission can be used to transmit as many 8-bit data words as needed, even configuring all characters in one continuous burst. to allow this, the saa6713h register auto-increment is re-addressing osdt_cdef after each write to osdt_cdef. any changes to the osd text ram definitions can also be made while the osd is displayed. so the usable character set is only limited by the size of the external microcontrollers rom. just keep in mind that due to internal address calculation, the font size (osdt_fr_x and osdt_fr_y) and the single colour start code (osdt_sc_lo and osdt_sc_hi) must be defined prior to any font definition, in order that the character data will not look disturbed.
2004 apr 05 72 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.14.2 osd bitmap the osd bitmap part can be used for displaying pixel based multicolour graphics along with the regular text based osm (see fig.22). its display position can be defined anywhere in the picture (osdb_px and osdb_py) and like the osd text it can be zoomed, flipped and rotated according to the settings within its control register osdb_ctrl0. it is allowed to overlap with a displayed osd text window if desired. in this event the bitmap_behind flag (osdb_ctrl0[6]) defines whether the bitmap part appears on top or behind the osd text information. two separate alpha-blending values (bg_alpha and fg_alpha) define a blending value for the osd bitmap and separate transparent flags provide the possibility to define either the foreground or the background from transparent to solid. the display colours are again defined on a separate osd_bitmap palette inside the osd_colour definition page 9 so each pixel can use one of the defined 16 colours where bitmap colour 0 is always treated as background. the osd bitmap uses an internal memory of 4 kbyte ram in which the graphic pixels are stored (see table 48). it can be parametrized freely in width (osdb_sx), height (osdb_sy) and colour depth (osdb_ctrl1[6:5], bits per pixel) with the restriction that the needed memory size still fits into the 4 kbyte memory address space. handbook, full pagewidth mhc229 picture osdb_sx (= 12) osdb_sy (= 11) osdb_px osdb_py fig.22 osd bitmap structure. table 48 bitmap ram con?gurations; note 1 note 1. x = dont care. bpp code used bits per pixel used colours displayable pixels example window sizes (not zoomed) 00 1 2 32768 256 128; 181 181 01 2 4 16384 256 64; 128 128 1x 4 16 8192 256 32; 90 90
2004 apr 05 73 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h the access to the graphic memory is based on a masked writing with pixel exact addressing (see fig.23) via the write cursor (osdb_cx, osdb_cy) always configuring 8 bits at a time (osdb_def) with data being processed from left to right and top to bottom. using the 8 corresponding mask bits (osdb_mask) any pixel within the osd bitmap can directly be accessed and redefined without changing neighbouring pixel also during display time allowing software guided animations for fancy start-up screens. both the osdb_def and osdb_mask are always msb aligned which means that bit 7 will be written to the pixel address that is referenced by the osd bitmap cursor (osdb_cx, osdb_cy). depending on the selected bitmap size and the number of colours to be used this pixel address will probable not be byte aligned but the user does not have to take care of any internal alignments. the next 8 bits that are written to osdb_def will be written bit wise starting with the msb from the given cursor location. in order to speed up the osd bitmap definitions the internal ram address is incremented by 8 bits always when a write to osdb_def happened. together with a stop of the saa6713h register auto-increment at this register, this allows a fast burst configuration of multiple pixel up to a complete osd bitmap definition setting the cursor to (0,0), the mask to ffh and writing all needed data bytes in a single burst. the number of needed byte transmissions is derived by multiplying the total number of pixels to be configured with the used bits per pixel and dividing this result by 8 bits. when overwriting parts of the bitmap image the user must handle the osdb_mask flags for the remaining bits that shall not overwrite any data by himself. handbook, full pagewidth start position of configuration: osdb_cx = 4, osdb_cy = 6 byte 1 byte 2 byte 3 byte 4 ... 1 bit per pixel 2 colour definition (bits per pixel code = 00) 2 bits per pixel 4 colour definition (bits per pixel code = 01) 4 bits per pixel 16 colour definition (bits per pixel code = 1x) byte 1 byte 2 byte byte 4 3 ... b1 b2 b3 b4 osd bitmap defined with osdb_sx = 14 and osdb_sy = 19 mhc230 fig.23 data format of the osd bitmap ram.
2004 apr 05 74 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.14.3 osd pointer the osd pointer icon is a four colour 32 32 pixel structure and is intended to be used as a cursor on top of an osm (see fig.24). it is very much alike the osd bitmap part allowing individual positioning (osdp_px_hi, osdp_px_lo, osdp_py_hi and osdp_py_lo), zooming, flipping and rotating (osdp_ctrl0) but will always be displayed on top of any osd text or osd bitmap window. it is fixed in its resolution and always uses 2 bits per pixel allowing 4 possible colours. those colours are again definable via a palette in the osd colour settings (register page 9) where colour 0 is always treated as background colour. the foreground and the background colours can be displayed from solid to almost transparent with an individual alpha-blending factor (osdp_fga and osdp_bga) or fully transparent using fg_trans and bg_trans flags inside the osdp_ctrl1 register. for animation purpose of the icon, it is double buffered and able to generate a frame based switching interrupt. the buffer to be displayed can either be selected manually via the buffer_sel flag (osdp_ctrl0[6]) or can be switched automatically on each generated interrupt (osdp_ctrl0[7]). during the display of one buffer all writes are redirected to the inactive buffer. the period of the animation interrupt can be adjusted with the osdp_ad register that defines the number of frames between two interrupts. the interrupt generation itself can be enabled with the anim_int_en flag (osdp_ctrl1[5]). the definition of the osd pointer ram is similar to the definitions of the osd bitmap ram. the data is written msb-aligned to the osdp_def register using 2 bits per pixel. it is written starting from the pixel-exact coordinates given with the osd pointer cursor (osdp_cx and osdp_cy). instead of using a masked writing the definition width giving the number of pixels that are used from the osdp_def register and written from the given start position can be set via the osdp_dw register. as in the preceding osd units also the osd pointer uses an auto-increment always setting the cursor to the following definition position on each write to osdp_def where the increment is depending on the actual used defwidth. together with stopped saa6713h register auto-increment at osdp_def, this allows a fast burst definition mode that needs 256 i 2 c-bus byte transmissions to define a complete pointer buffer (see table 49).
2004 apr 05 75 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc231 32 pixel 32 pixel single pixel definition with osdp_cx = 20, osdp_cy = 21 and osdp_dw = 00 ... burst definition data bytes with osdp_cx = 0, osdp_cy = 0 and osdp_dw = 11 fig.24 data format of the osd pointer. table 49 osd pointer de?nition width defwidth[1:0] pixels to be defined used bits from osdp_def needed transmissions for a complete buffer 00 1 7 and 6 1024 01 2 7 to 4 512 10 3 7 to 2 342 11 4 7 to 0 256
2004 apr 05 76 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.14.4 h ow to use osd 7.14.4.1 how to create a simple single colour osd text 1. define the desired font size you want to use (osdt_fr_x and osdt_fr_y). 2. if ram font is needed: set osdt_sc to logic 0, set osdt_cc_hi to logic 0, set osdt_mask to ffh and define as many characters as wished by sending the needed number of data bytes to osdt_cdef preferable using an i 2 c-bus burst transmission. 3. define the osd text window size (osdt_wx and osdt_wy), set the cursor to osdt_curx = 0 and osdt_cury = 0. 4. set osdt_mask to ffh forcing all data to be written, all data to be configured. 5. define the window content by all three osdt_prop registers defining the attributes, colours and charcodes. use an i 2 c-bus burst transmission to speed up the programming. 6. set the desired position and orientation and enable the osd text with text_on flag that resides in osdt_ctrl0. 7.14.4.2 how to make changes to a displayed osd text 1. just set the cursor to the desired position and set the desired mask and write mode. 2. overwrite the character by writing the new osdt_prop registers defining new attributes, colours or charcodes. 7.14.4.3 how to create fade-in and fade-out effects 1. define the desired elements of the osd text window to be alpha-blended. 2. modify the values of osdt_bga every few frames in the desired direction by a certain value. 7.14.4.4 how to display a company logo 1. define the osd bitmap part in the needed resolution and the available colour depth. 2. set the osdb cursor to 0,0; set osdb_mask to ffh. 3. send all needed bytes with the correct used bits per pixel to osdb_def register, preferable in a burst sequence and turn the osd bitmap on. 7.14.4.5 how to use pointer animation 1. set the osdp cursor to 0,0 and osdp_dw to 11. 2. define the desired animation speed via osdp_ad, enable the pointer animation interrupt and enable automatic switching. 3. on each interrupt send a 256 byte burst containing the next picture of the animations to osdp_def. it should be noted that this must be finished before the next interrupt arrives. 7.14.4.6 remarks on the con?guration of the osd the three osd parts can be used independently. if all three parts are turned off, the whole osd module will be bypassed and clocked down to reduce the power consumption. most of the registers of the osd can be reprogrammed during processing except some needed definition parameters e.g. the resolution and sizes that need to be defined at start-up in order to guarantee correct address calculations. before defining the font ram a valid font size, a valid charcode and a valid sc_startcode must be defined. a burst definition with new address calculations to the osd font ram is only possible either in the multicolour or the single colour area of the memory. so if both areas are to be defined you should define the ram in two bursts, one for the multicolour and one for the single colour characters. with some effort it is of course possible to write down a user-packed byte burst to speed up the software init that includes all the multicolour and single colour information and create the corresponding font size afterwards. if something is not displayed as expected, you should carefully check the write mode. data will only be accepted when all of the corresponding osdt_prop registers are written. to speed up clears or highlighting, the areafill function should be used. by setting the areafill_start bit, an area of the text window within the defined area boundaries is overwritten using the actual settings of osdt_prop[2:0] registers and the osdt_mask register.
2004 apr 05 77 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h the text shadow is generated over the whole osd and just displayed in the enabled characters. so it is not character bound. this means that a neighbouring non-shadowed character can throw part of its shadow in the shadow allowed character. also the text shadow is only able to work correct if the whole osd is inside the picture boundaries and will be turned off automatically if this is not the case. the generated shadow is treated as background, so the shadow is alpha-blended with the background alpha-blending factor, but the shadow is never displayed transparent. during any configuration with the cursors in either the osd window or one of the pixel addresses be aware that the cursor will wrap around if the calculated address exceeds the physical memory address space. 7.15 colour look-up table the colour look-up table unit (or gamma correction unit) performs gamma correction and colour component brightness and contrast adjustment. each 8-bit rgb component value is mapped to a programmable 10-bit value by using it as an index for a look-up table that returns the corresponding image value. the colour components are processed by three independent tables. the output value for each index value is programmed by writing the 8-bit index to register cl_index and then programming registers cl_value_hi (02h) and cl_value_lo (03h) with the 10-bit image value. each of the three look-up tables is individually activated for programming by setting red_prog, geen_prog or blue_prog respectively to logic 1. the activated tables are updated with the new value pair when the lower byte of cl_value_lo (03h) was written. to support quick programming of consecutive values, the index value is incremented after every completed write, so cl_index does not have to be reprogrammed for every data pair. also the i 2 c-bus subaddress auto-increment is overridden when writing to cl_value_lo. instead the subaddress for the next write is determined according to register cl_ctrl. if quick_prog is set logic 0 the subaddress for the next write is set back to 02h (cl_value_hi); otherwise it remains 03h (cl_value_lo), which allows sequential writes of the lower byte only. as the look-up tables can only be either written or read at the same time, during write operations with activated colour look-up the tables are bypassed. to avoid any influence on the output picture, write_hsynced can be set to logic 1 to update the look-up tables only during horizontal blanking, which slows down programming speed. colour look-up is enabled by setting cc_on to logic 1; otherwise the colour look-up tables are in bypass mode and the image values consist of the original value in the upper eight bits and both lsbs are set to logic 0. programming of the look-up tables is possible in bypass mode or during data processing. 7.16 dithering unit the dither unit improves the visual quality of displays with only 6-bit or 8-bit physical colour resolution to a virtual colour depth of 10 bits. this is achieved through temporal variation of the physically possible colour values. to reduce artefacts of the temporal variation neighbouring pixels follow different sequences of variation. the dithering unit registers are mapped to page 10, registers 80h to 83h. dithering is switched on if dither_bypass is set to logic 0; otherwise the dithering unit is bypassed. the colour depth of the target display is selected by dither_out_bits. for an 8-bit panel dither_out_bits is set to logic 1; for a 6-bit panel the programming bit is set to logic 0. bits dither_idx_ofs_reg[2:0] give a choice of variation sequences (see table 50). best quality is expected for most displays with the setting random. table 50 dithering sequences; note 1 note 1. x = dont care. additionally, the unit adds lsb noise to the 10-bit colour values from the colour look-up table, when enabled by dither_add_noise = 1, which improves visual display quality of certain 10-bit displays (e.g. plasma displays). the noise includes only one lsb if dither_noise_mag is set to logic 0; otherwise two lsbs. configuration parameters dither_colmap, dither_rand_mono and dither_rand_mode are for test purposes and should be left in their reset values. dither_idx_ofs_reg[2:0] sequence 000 constant zero 001 2 2 bayer 010 4 4 bayer 011 5 5 special 1xx random
2004 apr 05 78 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17 output interface the output interface (oif) provides picture data and command signals to the display. programming the output interface, the output frame geometry can be defined. as most displays require continuous data stream during one frame or line, it is possible to define wait points. there are different possibilities how to map the rgb data to the output ports pa to pf. the saa6713h does not have particular output ports for panel signals vsync, hsync or de. instead, there are in total 10 configurable signal generator (csg) outputs which are driven by free programmable csgs. all output interface programming registers are mapped to the i 2 c-bus configuration register page 11. 7.17.1 d efinition of the output frame geometry the total output frame area (main frame) is defined by blank_line_length and last_line (registers oi_fx and oi_fy). it consists of the visible data (active frame) and the invisible data (blanking); see fig.25 and table 51. the active frame is divided into border and picture area. the picture area includes the data from the input stream. the border area is around the picture area. if no border is needed, the register values of picture and active area have to be equal. the active frame can be put anywhere inside the main frame except in the first row or in the first column of the main frame. the geometric values for the frames/areas depend on the display and the timing. if the picture values are not correct data may be lost or missing data will be replaced by border colour. the serial output begins in the upper left corner of the main frame in row 1 and column 1. the active frame starts in row active_start_y and in column active_start_x (point a in fig.25). values 0 are not allowed and the active frame or the picture area cannot start in column one. the picture area has to be contained in the active frame, at maximum it may be identical to the active frame. handbook, full pagewidth mhc232 1,1 main frame active frame border area picture area last_line blank_line_length a b c d e fig.25 output frame set-up.
2004 apr 05 79 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h table 51 programmable geometric values to make timing adaption of output to input frame easier, each area has its own line length, i.e. the blanking behind the border area can be freely adjusted. as some panels are sensitive to different line lengths, they should differ as little as possible. all line length values have to be greater or equal to active_end_x. parameter active_end_x must be greater or equal to picture_end_x. the according programming registers are listed in table 52. border and blanking colour are freely programmable as described in table 53. table 52 line length values table 53 border and blanking colour point horizontal vertical a active_start_x (oi_asx) active_start_y (oi_asy) b picture_start_x (oi_psx) picture_start_y (oi_psy) c picture_end_x (oi_pex) picture_end_y (oi_pey) d active_end_x (oi_aex) active_end_y (oi_aey) e blank_line_length (oi_fx) last_line (oi_fy) area line length blanking blank_line_length (oi_fx) border active_line_length (oi_alx) picture picture_line_length (oi_px) area register blanking oi_blc_r, oi_blc_g and oi_blc_b border oi_boc_r, oi_boc_g and oi_boc_b
2004 apr 05 80 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.2 w ait modes it is not necessary to match the output timing exactly to the input timing. the output timing can be a little faster. in this event it may happen that no valid data is available at the oif. as the output stream to the panel should not be interrupted during the output of a frame or line, a line wise and a frame wise wait mode is available. the wait_column (register oi_wx) has to be programmed. during output of lines inside the picture area, the output stream stops at this defined wait_column and waits until new picture data is available. if fieldwise wait mode is programmed, the output only stops at the wait_column of the first line of the picture area. the wait_column must be located in front of the active area (see fig.26). additionally, there is a free-running mode without any wait point. the wait modes are programmed in register oi_wm according to table 54. handbook, full pagewidth mhc233 last_line 1,1 main frame active frame blank_line_length wait_column picture area waiting possible ?st row continuous picture data fig.26 wait column. table 54 wait modes wait_mode[1:0] mode action 11 free-running no waiting 10 01 row stop waiting in each row of picture area 00 one stop waiting in ?rst row of picture area once each frame
2004 apr 05 81 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.3 d ata to output mapping each colour of each pixel is handled separately. in double pixel mode there are 6 bytes (red, green and blue of pixel 0 and pixel 1 from which pixel 0 arrives first). in single pixel mode there are 3 bytes (red, green and blue of pixel 0). each of the six output ports (see fig.27) can be connected to each colour and can be inverted, swapped and aligned to the msb (sensible to drive 6-bit panels). registers oi_b0r, oi_b0g, oi_b0b, oi_b1r, oi_b1g and oi_b1b have to be programmed according to table 55. handbook, full pagewidth blank generation, border generation, transition minimizing msb lsb pa pb pc pd pe pf mhc234 r0 g0 b0 2 bits 6 bits r1 g1 b1 8 bits each 48 bits fig.27 data to output mapping schema. table 55 data to output mapping; note 1 note 1. x = dont care. bit function action msb_align alignment if this bit is set to logic 1, then the lower 6 bits are aligned to msb. swap swapping if this bit is set to logic 1, then swap [7:0] to [0:7]; lsb becomes msb. inv inversion if this bit is set to logic 1, then bit wise inversion of the colour component. port_x_conf[2:0] allocation output port px gets data byte with 6 bytes in double pixel mode or 3 bytes in single pixel mode (for x = a to f): 11x: 0r 101: 0g 100: 0b 01x: 1r 001: 1g 000: 1b
2004 apr 05 82 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.4 c onfigurable signal generators there are 10 configurable signal generators available. the functionality is particularly designed to drive displays directly without the use of a timing controller (tcon). for operation with hsync, vsync and data enable only three generators are needed. all csgs have the same basic structure (see fig.28). there are two programmable action points: the start point (a) and the end point (b). the start point describes the upper left corner of the operation window. the end point the lower right corner. when the row and line counter values of the output interface are equal to the action point values, the output becomes high or low according to the set-up. the possible actions for the start point are set or toggle and for the end point reset or toggle. the output signal can be inverted additionally. two modes are available: frame or line based. in frame based mode the signal only changes in the upper, left and the lower, right corner of each frame. in line based mode the signal changes every line at the beginning and at the end of the operation window. it is also possible to use just one action point, e.g. to toggle the output each line or just once in a frame. to disable an action point a logic 0 has to be programmed to the y-value. csg0 and csg1 are driven by two separate signal generators (csg0a or csg0b and csg1a or csg1b respectively) allowing a more complex signal to be generated. the operation window upper left corner (a) is defined by the oi_gxsx and oi_gxsy registers and the lower right corner (b) is described by the oi_gxex and oi_gxey registers (x out of 0 to 9). the action is defined by programming the configuration register oi_gxc. the corners (a and b) of the operation window are the action points. in each action point the output signal is modified as described in the configuration register. at the first action point (a) the output will be set or toggled. at the second action point the output signal will be reset or toggled again. example: in order to define a de signal, the csg window is set to the active area. bit frame or bit line of the concerned csg control register is set to line mode and the csg signal is set to logic 1 at point 1 and set to logic 0 at point 2 (see figs 29 and 30). important programming hint: the horizontal start values (x-values) of the action points describe the offset from the beginning of the line. if you want to start e.g. csg0 at (2,3) you have to program the values (1,3). if you want to stop the signal after (12,14) you have to program the values (12,14) so the signal changes its value at the end of position 12 (edge to position 13). an offset of 0 is not allowed. avoid using the same column as wait column. there are 4 groups of csgs. the csgs of each group have some other additional features. handbook, full pagewidth mhc235 1,1 main frame last_line blank_line_length operation window a b in line mode the signal will be repeated in every line in the operation window action point in frame and line mode additional action points in line mode fig.28 output frame set-up.
2004 apr 05 83 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc236 line based operation window start_point (a) end_point (b) 1,1 last_line frame based start_point (a) end_point (b) 1,1 last_line fig.29 examples for signal generator outputs. handbook, full pagewidth mhc237 frame based 1,1 start_point (a) hs line based t t hs hs hs hs hs hs hs hs hs end_point (b) end_point (b) 1,1 start_point (a) hs vs hs vs hs vs hs vs fig.30 examples for signal generator outputs.
2004 apr 05 84 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.5 s pecial features and csg groups 7.17.5.1 csg0 and csg1 these csgs are two csgs with one output (see fig.31). they are splitted in csgxa and csgxb. the a and b part are equal and the programming is as two separated csgs. so one can generate signals with four events each line/frame. 7.17.5.2 csg2 to csg5 normal csgs with two action points. additionally, csg2 plus csg3 and csg4 plus csg5 can cooperate like csg0/1 a/b on outputs csg3 and csg5. 7.17.5.3 csg6 and csg7 no special or additional features. two action points. 7.17.5.4 csg8 and csg9 these csgs have an additional action point. the signal can be set, reset or toggled in this point. the execution of action point 0 can be depressed only in line mode for every second line. the execution of action point 1 and 2 is not influenced by skip_mode. handbook, full pagewidth mhc238 frame based 1,1 hs line based t t hs hs hs hs hs hs hs hs hs 1,1 1,1 hs t hs hs hs hs set reset toggle hs vs hs vs hs vs hs vs hs vs hs vs fig.31 examples for csg0/1 outputs.
2004 apr 05 85 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.6 t ransition minimizing the transition minimizing programming is done in the oi_ctrl0 register in the oif. this section describes how the oif pixel input operates with inva and invb outputs for various values of ivsl0 and ivsl1 (register oi_ctrl0). all modes are designed for double pixel handling. 7.17.6.1 bit ivsl0 = 1 and bit ivsl1 = 0 inva operates with input pixel 0 (means the first of a couple). this inversion operation considers a total of 18 bits: the 6 high order bits of each colour component of input pixel 0 (r2 to r7, g2 to g7 and b2 to b7). the input data of time (n - 1) is compared to the data at time n. if 10 or more bits within the 18 bits have changed from low to high or from high to low, then inva toggles between high and low: if inva was high at (n - 1) it goes low, and if it was low at (n - 1), it toggles high. if 9 or fewer bits within the 18 bits have changed from high to low or from low to high, then inva does not toggle. when inva is high, all bits (24 bits) of pixel 0 to output (means data before data to output mapping) are inverted. invb operates with input pixel 1 (means the second of a couple). this inversion operation considers a total of 18 bits: the 6 high order bits of each colour component of input pixel 1 (r2 to r7, g2 to g7 and b2 to b7). the input data of time (n - 1) is compared to the data at time n. if 10 or more bits within the 18 bits have changed from low to high or from high to low, then invb toggles between high and low: if invb was high at (n - 1), it goes low, and if it was low at (n - 1), it toggles high. if 9 or fewer bits within the 18 bits have changed from high to low or from low to high, then invb does not toggle. when invb is high, all bits (24 bits) of pixel 1 to output are output inverted. 7.17.6.2 bit ivsl0 = 1 and bit ivsl1 = 1 inva and invb both operate with input pixel 0 and 1.this inversion operation considers a total of 36 bits, the 6 high order bits of each colour component of pixel 0 and 1 (0r2 to 0r7, 0g2 to 0g7, 0b2 to 0b7, 1r2 to 1r7, 1g2 to 1g7 and 1b2 to 1b7). the input data of time (n - 1) is compared to the data at time n. if 19 or more bits within the 36 bits have changed from low to high or from high to low, then both inva and invb toggle between high and low. when inva and invb are high at (n - 1), they go low, and when they are low at (n - 1), they toggle high. if 18 or fewer bits within the 36 bits have changed from high to low or from low to high, then inva and invb do not toggle. when inva and invb are both high, all bits (48 bits) are inverted. because there is no previous data for the first data in every column (horizontal period), the above noted toggle operations for inva and invb, as well as the data inversion operations are not performed. in the event of first data output of every column, inva and invb are set to low, and data is not inverted. 7.17.6.3 bit ivsl0 = 0 and bit ivsl1 = 0 for input pixel, data inversion is similar to when ivsl0 = 1, ivsl1 = 0, with input pixel 0 and 1 being separated, and the outputs being driven according to the results of calculations. for inva and invb signals, the calculations are similar to when ivsl0 = 1, ivsl1 = 0, but the inva and invb outputs are driven as logical opposites. 7.17.6.4 bit ivsl0 = 0 and bit ivsl1 = 1 the inva and invb signals are always driven low and data inversion operations are not performed. 7.17.7 b ackground and emergency frame generator the output interface includes a simple frame generator. it may be useful when the front-end receives no signal, so no front-end clock is available. the generated frame has the same dimensions as the picture area. the frame colour is programmable (oi_fcx). the on screen display is still working. the generator may be switched on via the oi_fc_en register.
2004 apr 05 86 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.8 g lobal control the output interface has four global modes, which can be programmed with bits oi_enable, power_down and blank_mode (register oi_ctrl0) according to table 56. the blank colour is programmable via bits blank_colour_red, blank_colour_green and blank_colour_blue. table 56 global modes; note 1 note 1. x = dont care. oi_ enable power_ down blank_ mode mode action 1 0 1 blank all colours replaced by blank colour values x 1 x power-down all registers set to default, like soft reset; all outputs low 0 0 x disable all outputs reset but incoming data queued to trash 1 0 0 normal normal operation 7.17.9 p anel clock the output interface can handle single and double pixel mode (bit double_pixel in register oi_ctrl1). in single pixel mode one pixel (24 bits) is available each cycle at the output ports. the panel clock pclk is the same as the back-end clock. in double pixel mode 2 pixels (48 bits) are available at the output ports. the pclk in double pixel mode changes every second cycle of the back-end clock. the panel clock polarity can be inverted by setting pclk_pol of register oi_ctrl1 to logic 1. at the beginning of each frame the pclk is synced again. it is very important that the number of pixels in a double pixel frame is even. the horizontal sync signal of the selected video input sources (dvi or vga) may be used as a reference clock for the panel pll (see table 57). this allows more stable locking of the panel timing to the source timing. in this mode the pll will be coasted during vertical sync when a composite sync or sync-on-green is enabled (iif_cs_sog_en = 1). table 57 panel pll 7.17.10 h ow to start the output interface table 58 starting output interface pll_src function 0 pre-divided clock 1 hs_pll (iif_dvi_on = 0) or hs_dvi (iif_dvi_on = 1) step action 1 set-up frame geometry 2 set-up signal generators 3 set-up wait column and wait mode 4 set-up pclk and pixel mode 5 enable output interface
2004 apr 05 87 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.11 p rogrammable output drive strength for all data and control signals of the output interface (pa[7:0], pb[7:0], pc[7:0], pd[7:0], pe[7:0], pf[7:0], csg[9:0], inva, invb, outen and pwm) a programmable output drive strength up to 15 ma is provided (in 8 steps and starting at 2.9 ma); see table 59. for the pclk output, a programmable output drive up to 30 ma is provided (in 8 steps and starting at 5.8 ma); see table 59. individual drive strength programming is possible for each 8-bit group of data signals (see table 60). the drive strength of control and clock signals are programmable individually. this is necessary to drive the multiple source and gate drivers directly. table 59 programmable drive strength ds2 ds1 ds0 data and control outputs (ma) pclk output (ma) 0 0 0 2.9 5.8 0 0 1 3.4 6.8 010 4 8 011 5 10 100 6 12 101 8 16 1 1 0 11 22 1 1 1 15 30 table 60 output interface drive strength bit description remark pin_drv_inva[2:0] output drive strength for inva from 2.9 ma (reset) to 15 ma; see table 59 pin_drv_invb[2:0] output drive strength for invb pin_drv_pa[2:0] output drive strength for pa pin_drv_pb[2:0] output drive strength for pb pin_drv_pc[2:0] output drive strength for pc pin_drv_pd[2:0] output drive strength for pd pin_drv_pe[2:0] output drive strength for pe pin_drv_pf[2:0] output drive strength for pf pin_drv_csg0[2:0] output drive strength for csg0 pin_drv_csg1[2:0] output drive strength for csg1 pin_drv_csg2[2:0] output drive strength for csg2 pin_drv_csg3[2:0] output drive strength for csg3 pin_drv_csg4[2:0] output drive strength for csg4 pin_drv_csg5[2:0] output drive strength for csg5 pin_drv_csg6[2:0] output drive strength for csg6 pin_drv_csg7[2:0] output drive strength for csg7 pin_drv_csg8[2:0] output drive strength for csg8 pin_drv_csg9[2:0] output drive strength for csg9 pin_drv_pwm[2:0] output drive strength for pwm pin_drv_outen[2:0] output drive strength for outen pin_drv_pclk[2:0] output drive strength for pclk from 5.8 ma (reset) to 30 ma; see table 59
2004 apr 05 88 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 7.17.12 a djustable output delays every output pin, except pin pwm, can be delayed. the delay increment is 0.36 ns. the programming value is 5-bit wide (see table 61). table 61 data to output mapping register bit output oi_inva_del inversion_a_pin_delay[4:0] inva oi_invb_del inversion_b_pin_delay[4:0] invb oi_pad pin_delay[4:0] pa oi_pbd pin_delay[4:0] pb oi_pcd pin_delay[4:0] pc oi_pdd pin_delay[4:0] pd oi_ped pin_delay[4:0] pe oi_pfd pin_delay[4:0] pf oi_ctrl1 pclk_pin_delay[4:0] pclk oi_g0bd pin_delay[4:0] csg0 oi_g1bd pin_delay[4:0] csg1 oi_g2d pin_delay[4:0] csg2 oi_g3d pin_delay[4:0] csg3 oi_g4d pin_delay[4:0] csg4 oi_g5d pin_delay[4:0] csg5 oi_g6d pin_delay[4:0] csg6 oi_g7d pin_delay[4:0] csg7 oi_g8d pin_delay[4:0] csg8 oi_g9d pin_delay[4:0] csg9 7.17.13 p ulse width modulation a pulse width modulated signal can be generated for brightness control of the panel. the pulse width and the pre-divider value can be programmed. the pwm can be synced with the h-gate. the logical polarity can be inverted. the pwm runs with the system clock and can be divided by the pre-divider. a period depends on 256 cycles. the configuration registers for the pwm are oi_pwm0 and oi_pwm1. 7.17.14 r eset behaviour a hardware reset forces all true bidirectional pins (pax, pbx, pcx, vclk, vsync, sda and hsda) to input. their output functionality must be explicitly invoked by software. csg2/a0 and csg4/a1 are input during the hardware reset for latching in the configuration data and switched to output immediately after hardware reset. 8 boundary scan test the saa6713h has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the saa6713h follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are: test mode select (tms), test clock (tck), test reset ( trst), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, intest, sample, clamp and idcode are all supported (see table 62). details about the jtag bst-test can be found in the specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) description of the saa6713h is available on request.
2004 apr 05 89 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 8.1 initialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset) when the ic is in the functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting pin trst to low. 8.2 device identi?cation codes a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between pins tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.32. table 62 bst instructions supported by the saa6713h instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. intest this optional instruction allows testing of the internal logic (no customer support available). user1 this private instruction allows testing by the manufacturer (no customer support available). handbook, full pagewidth mhc239 nnnn 0110 0111 0001 0011 0000 0010 101 4-bit version code 16-bit part number 11-bit manufacturer identification 1 31 msb lsb 28 27 12 10 tdo 11 tdi fig.32 32 bits of identification code.
2004 apr 05 90 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 9 limiting values in accordance with the absolute maximum rating system (iec 60134) notes 1. may not exceed 4.2 v; including outputs in 3-state mode; only when supply voltages are present. 2. human body model: c = 100 pf; r = 1.5 k w . 3. machine model: c = 200 pf; l = 0.75 m h; r = 0 w . 10 thermal characteristics symbol parameter conditions min. max. unit v ddd(ic) digital supply voltage for internal core on pins v ddd(ic1) to v ddd(ic6) - 0.5 +3.3 v v dda analog supply voltage on pins v dda(r) , v dda(g) , v dda(b) , v dda(adc)(r) , v dda(adc)(g) , v dda(adc)(b) and v dda(dvi1) to v dda(dvi3) 0 2.8 v v dd(pll) , v ddd(pll) , v dda(pll) supply voltage for pll on pins v dd(pll)(dvi) , v dd(pll)(p) , v dda(pll)(s) and v ddd(pll)(s) 0 2.8 v v dda(ib) analog supply voltage for input buffer on pin v dda(ib) 0 3.3 v v ddd(ep) external digital pad supply voltage for pins v ddd(ep1) to v ddd(ep10) - 0.5 +4.2 v v dda(ep) external analog pad supply voltage for pin v dda(ep) 0 3.6 v v n voltage on digital input pins sda and scl (5 v tolerant) - 0.5 +5.8 v digital input pins note 1 - 0.5 v ddd(ep) + 0.5 v analog input and output pins - 0.5 v dda + 0.5 v p tot total power dissipation - 1.8 w t stg storage temperature - 25 +150 c t j junction temperature - 125 c t amb ambient temperature 0 70 c v esd electrostatic discharge voltage note 2 - 1500 +2000 v note 3 - 150 +150 v m aximum ratings dvi interface v cc termination supply voltage - 4.0 v v i voltage on any signal wire - 0.5 +4.0 v r t termination resistance off chip 0 open-circuit w symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 26 k/w
2004 apr 05 91 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 11 characteristics t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies d igital supply for internal core : pins v ddd(ic1) to v ddd(ic6) v ddd(ic) supply voltage 2.3 2.5 2.7 v i ddd(ic) supply current note 1 - 110 - ma p ddd(ic) power dissipation note 1 - 275 - mw a nalog supply for dvi, colour channels and adc s : pins v dda(dvi1) to v dda(dvi3) ,v dda(r) ,v dda(g) ,v dda(b) , v dda(adc)(r) ,v dda(adc)(g) and v dda(adc)(b) v dda supply voltage 2.3 2.5 2.7 v i dda supply current note 1 - 240 - ma p dda power dissipation note 1 - 600 - mw s upply for pll: pins v dd(pll)(dvi) ,v dd(pll)(p) ,v dda(pll)(s) and v ddd(pll)(s) v dd(pll) supply voltage 2.3 2.5 2.7 v i dd(pll) supply current note 1 - 5 - ma p dd(pll) power dissipation note 1 - 13 - mw a nalog supply for input buffer : pin v dda(ib) v dda(ib) supply voltage 2.7 3.0 3.3 v i dda(ib) supply current note 1 - 2 - ma p dda(ib) power dissipation note 1 - 6 - mw d igital supply for pads : pins v ddd(ep1) to v ddd(ep10) v ddd(ep) supply voltage 3.0 3.3 3.6 v i ddd(ep) supply current note 1 - 50 - ma p ddd(ep) power dissipation note 1 - 165 - mw a nalog supply for pad : pin v dda(ep) v dda(ep) supply voltage 3.0 3.3 3.6 v i dda(ep) supply current note 1 - 1 - ma p dda(ep) power dissipation note 1 - 3 - mw analog front-end inputs a nalog video inputs : pins rin, gin and bin v i(p-p) input voltage (peak-to-peak value) note 2 0.2 - 0.5 v c i input capacitance - 850 - ff s ync - on - green slicer input : pin sogin v i(p-p) input voltage (peak-to-peak value) 0.1 - 0.4 v
2004 apr 05 92 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h a nalog - to - digital converter f pixel sample clock of adc 25 - 110 mhz n resolution of adc - 8 - bits le dc(i) dc integral linearity error - 0.8 - lsb le dc(d) dc differential linearity error - 1.6 - lsb enob effective number of bits f pixel = 110 mhz 6.6 7 - bits c ontrol loops for contrast and brightness m matching of contrast and clamp settings among the three channels - 1 - % b loop bandwidth of contrast and clamp loops - 500 - hz n clamp required width of clamp pulse 40 -- pixels n gainc required width of gain control pulse 96 -- pixels dvi inputs differential input pairs : pins rxcp and rxcn, rx0p and rx0n, rx1p and rx1n and rx2p and rx2n v cc termination supply voltage note 3 3.13 3.3 3.46 v r t external termination resistance 45 50 55 w v i(cm) common mode dc input voltage note 4 v cc - 0.3 - v cc - 0.037 v v i(se) single-ended (high) dc input voltage when disconnected v cc - 0.01 v cc v cc + 0.01 v v i(diff)(p-p) differential input voltage (peak-to-peak value) note 4 150 - 1560 mv s intra-pair skew 0.4 -- tbit t r rise time 75 -- ps f clk clock frequency 25.175 - 110 mhz digital inputs c lock , reset and bst inputs : pins clk, rst, tck, tdi, tms and trst v il low-level input voltage 0 - 0.7 v v ih high-level input voltage 1.7 - v ddd(ep) v i il low-level input current -- 1 m a i ih high-level input current -- 1 m a c i input capacitance -- 8pf h orizontal sync input : pin hsync (5 v tolerant ) v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - 5.5 v i il low-level input current -- 1 m a i ih high-level input current -- 1 m a c i input capacitance -- 8pf symbol parameter conditions min. typ. max. unit
2004 apr 05 93 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h output pins d ata ports and panel control signals : pins pd0 to pd7, pe0 to pe7, pf0 to pf7, csg0, csg1, csg3, csg5 to csg9, inva, invb, pclk, pwm and outen v ol low-level output voltage i ol =16ma -- 0.4 v v oh high-level output voltage i oh = - 16 ma v ddd(ep) - 0.4 -- v i pu pull-up current v i =0 - 23 - 50 - 65 m a v dd 2004 apr 05 94 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h notes 1. 1024 768 at 60 hz with input pattern grill_33. 2. pin connected to video source via a 6 db/75 w attenuator. 3. the input circuits are able to cope with the common mode input voltages that are above the supply voltage of the saa6713h (2.5 v). 4. characteristics apply to all data input pairs and the clock input pair. 5. leakage current due to external voltage higher than internal v dd . 6. minimum value for v i = 4.5 v; maximum value for v i = 5.5 v. i 2 c-bus interface c lock input : pins scl and hscl v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 5 v tolerant 2.0 - 5.5 v v hys hysteresis voltage 0.3 -- v i il low-level input current -- 1 m a i ih high-level input current -- 1 m a c i input capacitance -- 8pf d ata input and output : pin sda v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 5 v tolerant 2.0 - 5.5 v v hys hysteresis voltage 0.3 -- v v ol low-level output voltage i ol =4ma 0 - 0.4 v d ata input and output : pin hsda v il low-level input voltage 0 - 0.3v ddd(ep) v v ih high-level input voltage 5 v tolerant 0.7v ddd(ep) - 5.5 v v hys hysteresis voltage 0.05v ddd(ep) -- v v ol low-level output voltage i ol =3ma 0 - 0.4 v symbol parameter conditions min. typ. max. unit
2004 apr 05 95 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 12 timing characteristics symbol parameter conditions min. typ. max. unit system clock input at pin clk t cy system clock cycle time 20 - 41.66 ns analog video interface; see fig.33 t cy analog video clock cycle time 9.1 -- ns t su video data set-up time 4 -- ns t h video data hold time 3 -- ns t vsync vertical sync length 2/f vclk -- ns t hsync horizontal sync length 2/f vclk -- ns parallel video interface; see fig.34 t cy parallel video clock cycle time 9.1 -- ns t su video data set-up time 0 -- ns t h video data hold time 5 -- ns panel interface; see fig.35 t cy panel clock cycle time 15.4 - 40 ns t out1 undelayed pclk to output delay time; single pixel mode c l =15pf - 2.5 - +0.2 ns t out2 undelayed pclk to output delay time; double pixel mode c l =15pf - 3.5 -- 0.8 ns t del output delay increment 200 500 800 ps handbook, full pagewidth mhc240 t cy vclk hsync, vsync t su t h fig.33 analog video interface timing.
2004 apr 05 96 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h handbook, full pagewidth mhc241 t cy vclk pa, pb, pc t su t h fig.34 parallel video interface timing. handbook, full pagewidth mhc242 t cy pclk delayed pa, pb, pc, pd, pe, pf, inva, invb, csg undelayed, single pixel mode pa, pb, pc, pd, pe, pf, inva, invb, csg undelayed, double pixel mode t out1 t out2 t out + n t del fig.35 panel interface timing.
2004 apr 05 97 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 13 application information handbook, full pagewidth mhc243 i 2 c-bus i 2 c-bus (hdcp) eeprom dvi port vga port usb microcontroller saa6713h panel connector fig.36 application board block diagram.
2004 apr 05 98 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 14 package outline unit a 1 a 2 a 3 b p ce (1) (1) (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.50 0.25 3.6 3.2 0.25 0.38 0.22 0.23 0.13 28.1 27.9 0.65 0.3 1.6 1.5 1.1 7 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.03 0.73 sot322-2 135e12 ms-022 00-01-19 03-02-25 d (1) 28.1 27.9 h d 31.45 30.95 31.45 30.95 e z 1.5 1.1 d pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 40 c d h b p e h a 2 v m b d z d a z e e v m a x 1 160 121 120 81 80 41 y w m w m 0 5 10 mm scale sot322-2 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height qfp160: plastic quad flat package; a max. 4.07
2004 apr 05 99 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 15 soldering 15.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 15.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 220 c (snpb process) or below 245 c (pb-free process) C for all bga and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 235 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2004 apr 05 100 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 15.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, ssop-t (3) , tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable pmfp (8) not suitable not suitable
2004 apr 05 101 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 16 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 17 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 apr 05 102 philips semiconductors product speci?cation xga dual input ?at panel controller saa6713h 19 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004 sca76 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r21/02/pp103 date of release: 2004 apr 05 document order number: 9397 750 12101

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